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Difference between revisions of "arm holdings/microarchitectures/cortex-a5"
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(Key changes from {{\\|Cortex-A9}})
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== Architecture ==
 
== Architecture ==
 
=== Key changes from {{\\|Cortex-A9}} ===
 
=== Key changes from {{\\|Cortex-A9}} ===
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* New [[in-order]] pipeline (form [[out-of-order]])
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** Shorter [[pipeline]] (8, up from 9-12)
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** Single-issue (from [[dual-issue]])
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* Reduced return stack size (4 entries, down from 8)
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* Integer
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** Hardware [[Fused Multiply-Accumulate]]
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* [[VFPv4]] (from [[VFPv3]])
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{{expand list}}
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=== Block Diagram ===
 
=== Block Diagram ===
 
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{{empty section}}

Revision as of 00:33, 31 December 2018

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Cortex-A5 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionOctober 22, 2009
Succession

Cortex-A5 (codename Sparrow) is the successor to the Cortex-A9, an ultra-low power ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.

Architecture

Key changes from Cortex-A9

This list is incomplete; you can help by expanding it.

Block Diagram

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Memory Hierarchy

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Licensees

Arm named the following companies as licensees.

codenameCortex-A5 +
designerARM Holdings +
first launchedOctober 22, 2009 +
full page namearm holdings/microarchitectures/cortex-a5 +
instance ofmicroarchitecture +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-A5 +