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Difference between revisions of "mediatek/helio/mt6799"
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{{mediatek title|Helio X30}}
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{{mediatek title|Helio X30 (MT6799)}}
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{{mpu
+
{{chip
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| future              = Yes
+
|name=MediaTek Helio X30
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| name               = MediaTek Helio X30
+
|no image=Yes
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| no image           = yes
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|designer=MediaTek
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| image              =
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|designer 2=ARM Holdings
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| image size          =
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|manufacturer=TSMC
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| caption            =  
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|model number=Helio X30
−
| designer           = MediaTek
+
|part number=MT6799
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| designer 2         = ARM Holdings
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|market=Mobile
−
| manufacturer       = TSMC
+
|market 2=Embedded
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| model number       = Helio X30
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|first announced=September 26, 2016
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| part number         =
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|first launched=February 27, 2017
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| part number 2      =  
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|family=Helio
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| market             = Mobile
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|series=Helio X
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| market 2           = Embedded
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|frequency=2,500 MHz
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| first announced     = September 26, 2016
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|frequency 2=2,200 MHz
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| first launched     = 2017
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|frequency 3=1,900 MHz
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| last order          =
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|bus type=AMBA 4 AXI
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| last shipment      =
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|isa=ARMv8
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| release price      =
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|isa family=ARM
−
 
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|microarch=Cortex-A53
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| family             = Helio
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|microarch 2=Cortex-A73
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| series             = Helio X
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|microarch 3=Cortex-A35
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| locked              =
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|core name=Cortex-A35
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| frequency           = 2,800 MHz
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|core name 2=Cortex-A53
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| frequency 2         = 2,200 MHz
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|core name 3=Cortex-A73
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| frequency 3         = 2,000 MHz
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|process=10 nm
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| bus type           = AMBA 4 AXI
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|technology=CMOS
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| bus speed          =  
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|word size=64 bit
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| bus rate            =
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|core count=10
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| bus links          =
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|thread count=10
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| clock multiplier    =
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|max cpus=1
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|max memory=8 GiB
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| isa family         = ARM
 
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| isa                = ARMv8
 
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| microarch           = Cortex-A53
 
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| microarch 2         = Cortex-A73
 
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| platform            =  
 
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| chipset            =  
 
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| core name           = Cortex-A53
 
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| core name 2        = Cortex-A73
 
−
| core family        =
 
−
| core model          =
 
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| core stepping      =
 
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| process             = 10 nm
 
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| transistors        =
 
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| technology         = CMOS
 
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| die area            = <!-- XX mm² -->
 
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| die width          =
 
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| die length          =
 
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| word size           = 64 bit
 
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| core count         = 10
 
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| thread count       = 10
 
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| max cpus           = 1
 
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| max memory         =
 
−
 
 
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| electrical          =
 
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| power              =
 
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| v core              =
 
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| v core tolerance    =
 
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| v io                =
 
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| v io 2              =
 
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| v io 3              =
 
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| sdp                =
 
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| tdp                =
 
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| tdp typical        =
 
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| ctdp down          =
 
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| ctdp down frequency =
 
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| ctdp up            =
 
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| ctdp up frequency  =
 
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| temp min            =
 
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| temp max            =
 
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| tjunc min          =
 
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| tjunc max          =
 
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| tcase min          =
 
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| tcase max          =
 
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| tstorage min        = <!-- °C -->
 
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| tstorage max        =
 
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| tambient min        =
 
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| tambient max        =
 
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| packaging          =
 
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| package 0          =
 
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| package 0 type      =
 
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| package 0 pins      =
 
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| package 0 pitch    =
 
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| package 0 width    =
 
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| package 0 length    =
 
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| package 0 height    =  
 
 
}}
 
}}
−
'''Helio X30''' is a {{arch|64}} [[deca-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and set to be launched in early [[2017]]. This SoC incorporates 3 independent clusters of cores (called "Tri-Cluster" by MediaTek) operating at varying degrees of performance designed for certain workloads (operating at 2 GHz, 2.2 GHz, and 2.8 GHz) and supports dual-channel LPDDR3-1866. This SoC also incorporates a {{imgtec|PowerVR GT7400}} [[IGP]] operating at 870 MHz. The chip has a modem supporting [[LTE]] User Equipment (UE) category 10.
+
'''Helio X30''' ('''MT6799''') is a {{arch|64}} [[deca-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and launched in early [[2017]]. This SoC incorporates 3 independent clusters of cores (called "Tri-Cluster" by MediaTek) operating at varying degrees of performance designed for certain workloads (operating at 1.9 GHz, 2.2 GHz, and 2.5 GHz) and supports up to 8 GiB of quad-channel LPDDR4X-3732 memory. This SoC also incorporates a {{imgtec|PowerVR GT7400 Plus}} [[IGP]] operating at 800 MHz. The chip has a modem supporting [[LTE]] User Equipment (UE) category 10.
  
−
 
−
{{unknown features}}
 
 
== Architecture ==
 
== Architecture ==
 
The Helio X30 is designed is composed of 3 individual clusters of CPU cores depending on the level of performance required by the active applications.
 
The Helio X30 is designed is composed of 3 individual clusters of CPU cores depending on the level of performance required by the active applications.
  
−
* Extreme Performance - 2x {{armh|Cortex-A73|l=arch}} @ 2.8 GHz
+
* Extreme Performance - 2x {{armh|Cortex-A73|l=arch}} @ 2.5 GHz
 
* Performance/Power Balance - 4x {{armh|Cortex-A53|l=arch}} @ 2.2 GHz
 
* Performance/Power Balance - 4x {{armh|Cortex-A53|l=arch}} @ 2.2 GHz
−
* Power Efficiency - 4x {{armh|Cortex-A53|l=arch}} @ 2 GHz
+
* Power Efficiency - 4x {{armh|Cortex-A35|l=arch}} @ 1.9 GHz
  
 
The three clusters are designed as a modified {{armh|big.LITTLE}} configuration.
 
The three clusters are designed as a modified {{armh|big.LITTLE}} configuration.
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== Memory controller ==
 
== Memory controller ==
 
{{memory controller
 
{{memory controller
−
|type=LPDDR3-1866
+
|type=LPDDR4X-3732
 
|ecc=No
 
|ecc=No
 
|max mem=8 GiB
 
|max mem=8 GiB
 
|controllers=1
 
|controllers=1
−
|channels=2
+
|channels=4
 +
|width=16 bit
 
|max bandwidth=27.81 GiB/s
 
|max bandwidth=27.81 GiB/s
−
|bandwidth schan=13.9 GiB/s
+
|bandwidth schan=6.95 GiB/s
−
|bandwidth dchan=27.81 GiB/s
+
|bandwidth dchan=13.9 GiB/s
 +
|bandwidth qchan=27.81 GiB/s
 
}}
 
}}
  
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| max displays        =  
 
| max displays        =  
 
| max memory          =  
 
| max memory          =  
−
| frequency          = 870 MHz
+
| frequency          = 800 MHz
  
 
| output dsi          = Yes
 
| output dsi          = Yes
  
−
| max res dsi        = 2560x1600
+
| max res dsi        = 3840x2160
  
 
| direct3d ver        = 11.2
 
| direct3d ver        = 11.2
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== Utilizing devices ==
 
== Utilizing devices ==
−
<!--
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* [[used by::Meizu Pro 7]]
−
* [[used by::xxxxxxxxxxxxxxxxxxxxxx]]
+
* [[used by::Meizu Pro 7 Plus]]
−
-->
 
 
{{expand list}}
 
{{expand list}}
 +
 +
== Die ==
 +
* [[10 nm process]]
 +
 +
:[[File:x30 die shot.png|500px]]
 +
 +
== Bibliography ==
 +
* Mair, Hugh, et al. "3.4 A 10nm FinFET 2.8 GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance." Solid-State Circuits Conference (ISSCC), 2017 IEEE International. IEEE, 2017.

Latest revision as of 15:22, 29 December 2018

Edit Values
MediaTek Helio X30
General Info
DesignerMediaTek,
ARM Holdings
ManufacturerTSMC
Model NumberHelio X30
Part NumberMT6799
MarketMobile, Embedded
IntroductionSeptember 26, 2016 (announced)
February 27, 2017 (launched)
General Specs
FamilyHelio
SeriesHelio X
Frequency2,500 MHz, 2,200 MHz, 1,900 MHz
Bus typeAMBA 4 AXI
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCortex-A53, Cortex-A73, Cortex-A35
Core NameCortex-A35, Cortex-A53, Cortex-A73
Process10 nm
TechnologyCMOS
Word Size64 bit
Cores10
Threads10
Max Memory8 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)

Helio X30 (MT6799) is a 64-bit deca-core ARM LTE system on a chip designed by MediaTek and launched in early 2017. This SoC incorporates 3 independent clusters of cores (called "Tri-Cluster" by MediaTek) operating at varying degrees of performance designed for certain workloads (operating at 1.9 GHz, 2.2 GHz, and 2.5 GHz) and supports up to 8 GiB of quad-channel LPDDR4X-3732 memory. This SoC also incorporates a PowerVR GT7400 Plus IGP operating at 800 MHz. The chip has a modem supporting LTE User Equipment (UE) category 10.

Architecture[edit]

The Helio X30 is designed is composed of 3 individual clusters of CPU cores depending on the level of performance required by the active applications.

The three clusters are designed as a modified big.LITTLE configuration.

Cache[edit]

Main articles: Cortex-A53 § Cache and Cortex-A73 § Cache
New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4X-3732
Supports ECCNo
Max Mem8 GiB
Controllers1
Channels4
Width16 bit
Max Bandwidth27.81 GiB/s
28,477.44 MiB/s
29.861 GB/s
29,860.76 MB/s
0.0272 TiB/s
0.0299 TB/s
Bandwidth
Single 6.95 GiB/s
Double 13.9 GiB/s
Quad 27.81 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
USB
Revision2.0, 3.0
Ports8
UART
GP I/OYes


Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR GT7400 Plus
DesignerImagination Technologies
Frequency800 MHz
0.8 GHz
800,000 KHz
OutputDSI
Max Resolution
DSI3840x2160
Standards
Direct3D11.2
OpenGL3.3
OpenCL2.0
OpenGL ES3.2
Vulkan1.0

Wireless[edit]

Antu network-wireless-connected-100.svgWireless Communications
Wi-Fi
WiFi
802.11acYes
Cellular
2G
CSD Yes
GSM Yes
GPRS Yes
EDGE Yes
3G
UMTS
TD-SCDMAYes
DC-HSDPAYes
HSUPAYes
CDMA2000
1XYes
1xEV-DOYes
4G
LTE Advanced
E-UTRANYes
UE Cat10

Image[edit]

  • Integrated image signal processor supports 28 MP
  • Supports image stabilization
  • Supports video stabilization
  • Supports noise reduction
  • Supports lens shading correction
  • Supports AE/AWB/AF
  • Supports edge enhancement
  • Supports face detection and visual tracking
  • Hardware JPEG encoder

Video[edit]

  • Video encoding 4K2K @ 30fps with H.265 and HDR
  • Video decoding 4K2K @ 30fps, h.264, h.265 / HEVC, MPEG-1/2/4, VC-1, VP-8, VP-9

Audio[edit]

  • Audio content sampling rates 8kHz to 192kHz
  • Audio content sampling format 8-bit/16-bit/24-bit Mono/Stereo
  • I2S, PCM
  • Encode: AMR-NB, AMR-WB, AAC, OGG, ADPCM
  • Decode: WAV, MP3, MP2, AAC, AMR-NB, AMR-WB, MIDI, Vorbis, APE, AAC-plus v1, AAC-plus v2, FLAC, WMA, ADPCM
  • 7.1 channel MHL output

Utilizing devices[edit]

  • Meizu Pro 7
  • Meizu Pro 7 Plus

This list is incomplete; you can help by expanding it.

Die[edit]

x30 die shot.png

Bibliography[edit]

  • Mair, Hugh, et al. "3.4 A 10nm FinFET 2.8 GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance." Solid-State Circuits Conference (ISSCC), 2017 IEEE International. IEEE, 2017.
Retrieved from "https://en.wikichip.org/w/index.php?title=mediatek/helio/mt6799&oldid=85359"
Facts about "Helio X30 (MT6799) - MediaTek"
RDF feed
has 2g supporttrue +
has 3g supporttrue +
has 4g supporttrue +
has cdma2000 1x supporttrue +
has cdma2000 1xev-do supporttrue +
has cdma2000 supporttrue +
has csd supporttrue +
has dc-hsdpa supporttrue +
has e-utran supporttrue +
has ecc memory supportfalse +
has edge supporttrue +
has gprs supporttrue +
has gsm supporttrue +
has hsupa supporttrue +
has lte advanced supporttrue +
has td-scdma supporttrue +
has umts supporttrue +
integrated gpuPowerVR GT7400 Plus +
integrated gpu base frequency800 MHz (0.8 GHz, 800,000 KHz) +
integrated gpu designerImagination Technologies +
max memory bandwidth27.81 GiB/s (28,477.44 MiB/s, 29.861 GB/s, 29,860.76 MB/s, 0.0272 TiB/s, 0.0299 TB/s) +
max memory channels2 +
supported memory typeLPDDR4-1866 +
user equipment category10 +