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'''Cortex-A72''' (codename '''Maya''') is the successor to the {{armh|Cortex-A57|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A72, which implemented the {{arm|ARMv8}} ISA, is the a performant core which is often combined with a number of lower power cores (e.g. {{\\|Cortex-A53}}) in a {{armh|big.LITTLE}} configuration to achieve better energy/performance.
 
'''Cortex-A72''' (codename '''Maya''') is the successor to the {{armh|Cortex-A57|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A72, which implemented the {{arm|ARMv8}} ISA, is the a performant core which is often combined with a number of lower power cores (e.g. {{\\|Cortex-A53}}) in a {{armh|big.LITTLE}} configuration to achieve better energy/performance.
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== Architecture ==
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=== Key changes from {{\\|Cortex-A15}} ===
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{{empty section}}
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=== Block Diagram ===
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{{empty section}}
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=== Memory Hierarchy ===
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{{empty section}}
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== Die ==
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=== MediaTek [[Helio X20]] ===
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* TSMC [[20 nm process]]
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* 100 mm² die size
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* Quad-core ULP {{\\|Cortex-A53}}
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** ~21.81 mm² per cluster
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*** ~4.23 mm² per core
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* Quad-core efficient {{\\|Cortex-A53}}
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** ~29.73 mm² per cluster
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*** ~5.41 mm² per core
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* Dual-core High-performance Cortex-A72 +  1 MiB L2
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** ~27.36 mm² per cluster
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*** ~ 9.60 mm² per core
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*** ~ 7.50 mm² for 1 MiB L2
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 +
 +
:[[File:mt6797 die.png|600px]]

Revision as of 05:34, 29 December 2018

Edit Values
Cortex-A72 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionApril 23, 2015
Succession

Cortex-A72 (codename Maya) is the successor to the Cortex-A57, a low-power high-performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A72, which implemented the ARMv8 ISA, is the a performant core which is often combined with a number of lower power cores (e.g. Cortex-A53) in a big.LITTLE configuration to achieve better energy/performance.

Architecture

Key changes from Cortex-A15

New text document.svg This section is empty; you can help add the missing info by editing this page.

Block Diagram

New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory Hierarchy

New text document.svg This section is empty; you can help add the missing info by editing this page.

Die

MediaTek Helio X20

  • TSMC 20 nm process
  • 100 mm² die size
  • Quad-core ULP Cortex-A53
    • ~21.81 mm² per cluster
      • ~4.23 mm² per core
  • Quad-core efficient Cortex-A53
    • ~29.73 mm² per cluster
      • ~5.41 mm² per core
  • Dual-core High-performance Cortex-A72 + 1 MiB L2
    • ~27.36 mm² per cluster
      • ~ 9.60 mm² per core
      • ~ 7.50 mm² for 1 MiB L2


mt6797 die.png
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Facts about "Cortex-A72 - Microarchitectures - ARM"
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codenameCortex-A72 +
designerARM Holdings +
first launchedApril 23, 2015 +
full page namearm holdings/microarchitectures/cortex-a72 +
instance ofmicroarchitecture +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-A72 +