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Difference between revisions of "arm holdings/microarchitectures/poseidon"
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'''Poseidon''' is the successor to {{\\|Zeus}}, a high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the server market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
 
'''Poseidon''' is the successor to {{\\|Zeus}}, a high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the server market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
  
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== History ==
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[[File:arm server roadmap techcon 2018.jpg|thumb|right|Arm's server roadmap.]]
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Poseidon was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote.
  
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== Release Dates ==
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Ares is expected to show up in products around 2021.
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== Process Technology ==
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Zeus specifically designed takes advantage of the power and area advantages of the [[5nm process]].
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== Architecture ==
 
{{future information}}
 
{{future information}}
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* [[5 nm process]] (from [[7nm]])
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{{expand list}}
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== Bibliography ==
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* Drew Henry keynote, TechCon 2018 keynote.

Revision as of 17:17, 15 December 2018

Edit Values
Ares µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
Pipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Succession

Poseidon is the successor to Zeus, a high-performance ARM microarchitecture designed by ARM Holdings for the server market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.

History

Arm's server roadmap.

Poseidon was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote.

Release Dates

Ares is expected to show up in products around 2021.

Process Technology

Zeus specifically designed takes advantage of the power and area advantages of the 5nm process.

Architecture

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

This list is incomplete; you can help by expanding it.

Bibliography

  • Drew Henry keynote, TechCon 2018 keynote.
codenameAres +
designerARM Holdings +
full page namearm holdings/microarchitectures/poseidon +
instance ofmicroarchitecture +
manufacturerTSMC +
microarchitecture typeCPU +
nameAres +