Semiconductor & Computer Engineering
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== Overview == | == Overview == | ||
| − | The {{arm|ARMv8.5}} ISA introduces the memory Tagging Extension (MTE) which allows tags to be assigned to each memory allocation. Consequently, all memory accesses must then be made via a pointer with the correct tag. Memory accesses that use incorrect tags will tap, allowing the operating system to choose the course of action. It's worth noting that the MTE pointer tags use the existing ARM ISA feature that is also used by the {{arm|Pointer Authentication}} (PA) extension. This means that when both features are enabled, the {{arm|PAC}} size is reduced by eight bits to accommodate MTE. | + | The {{arm|ARMv8.5}} ISA introduces the memory Tagging Extension (MTE) which allows tags to be assigned to each memory allocation. Consequently, all memory accesses must then be made via a pointer with the correct tag. Memory accesses that use incorrect tags will tap, allowing the operating system to choose the course of action. MTE uses a 4-bit tag for every 16 bytes of memory. It's worth noting that the MTE pointer tags use the existing ARM ISA feature that is also used by the {{arm|Pointer Authentication}} (PA) extension. This means that when both features are enabled, the {{arm|PAC}} size is reduced by eight bits to accommodate MTE. |
== Instructions == | == Instructions == | ||
Revision as of 14:53, 8 December 2018
| ARM ISA | |
| General | |
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| Extensions | |
| Topics | |
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Memory tagging extension (MTE, MemTag, ARMv8.5-MemTag) is an ARM extension that enables hardware-assisted memory tagging. MTE was introduced with the ARMv8.5 ISA. MTE is an optional extension.
Overview
The ARMv8.5 ISA introduces the memory Tagging Extension (MTE) which allows tags to be assigned to each memory allocation. Consequently, all memory accesses must then be made via a pointer with the correct tag. Memory accesses that use incorrect tags will tap, allowing the operating system to choose the course of action. MTE uses a 4-bit tag for every 16 bytes of memory. It's worth noting that the MTE pointer tags use the existing ARM ISA feature that is also used by the Pointer Authentication (PA) extension. This means that when both features are enabled, the PAC size is reduced by eight bits to accommodate MTE.
Instructions
MTE introduces 16 new instructions for working with tagged memory:
| Instruction | Name | Format |
|---|---|---|
ADDG |
Add with Tag | ADDG <Xd/SP>, <Xn/SP>, #<uimm6>, #<uimm4>
|
CMPP |
Compare with Tag | CMPP <Xn/SP>, <Xm/SP>
|
GMI |
Tag Mask Insert | GMI <Xd>, <Xn/SP>, <Xm>
|
IRG |
Insert Random Tag | IRG <Xd/SP>, <Xn/SP>{, <Xm>}
|
LDG |
Load Allocation Tag | LDG <Xt>, [<Xn/SP>{, #<simm>}]
|
LDGV |
Load Tag Vector | LDGV <Xt>, [<Xn/SP>]!
|
ST2G |
Store Allocaton Tags | ST2G [<Xn/SP>], #<simm>ST2G [<Xn/SP>, #<simm>]!
|
STG |
Store Allocation Tag | STG [<Xn/SP>], #<simm>STG [<Xn/SP>, #<simm>]!STG [<Xn/SP>{, #<simm>}]
|
STGP |
Store Allocation Tag and Pair | STGP <Xt1>, <Xt2>, [<Xn/SP>], #<imm>STGP <Xt1>, <Xt2>, [<Xn/SP>, #<imm>]!STGP <Xt1>, <Xt2>, [<Xn/SP>{, #<imm>}]
|
STGV |
Store Tag Vector | STGV <Xt>, [<Xn/SP>]!
|
STZ2G |
Store Allocation Tags, Zeroing | STZ2G [<Xn/SP>], #<simm>STZ2G [<Xn/SP>, #<simm>]!STZ2G [<Xn/SP>{, #<simm>}]
|
STZG |
Store Allocation Tag, Zeroing | STZG [<Xn/SP>], #<simm>STZG [<Xn/SP>, #<simm>]!STZG [<Xn/SP>{, #<simm>}]
|
SUBG |
Subtract with Tag | SUBG <Xd/SP>, <Xn/SP>, #<uimm6>, #<uimm4>
|
SUBP |
Subtract Pointer | SUBP <Xd>, <Xn/SP>, <Xm/SP>
|
SUBPS |
Subtract Pointer, setting Flags | SUBPS <Xd>, <Xn/SP>, <Xm/SP>
|
See also
- SPARC's Application Data Integrity (ADI)