From WikiChip
Difference between revisions of "intel/celeron/n3060"
< intel‎ | celeron

 
(10 intermediate revisions by 4 users not shown)
Line 1: Line 1:
 
{{intel title|Celeron N3060}}
 
{{intel title|Celeron N3060}}
−
{{mpu
+
{{chip
−
| name               = Intel Celeron N3060
+
|name=Intel Celeron N3060
−
| no image           = Yes
+
|no image=Yes
−
| manufacturer       = Intel
+
|designer=Intel
−
| model number       = N3060
+
|manufacturer=Intel
−
| part number         = FH8066501715929
+
|model number=N3060
−
| part number 1      =  
+
|part number=FH8066501715929
−
| part number 2      =
+
|s-spec=SR2KN
−
| part number 3      =  
+
|s-spec qs=QK0J
−
| market             = Mobile
+
|market=Mobile
−
| first announced     = January 15, 2016
+
|first announced=January 15, 2016
−
| first launched     = January 15, 2016
+
|first launched=January 15, 2016
−
| last order          =  
+
|release price=$107.00
−
| last shipment      =
+
|family=Celeron
−
 
+
|series=N3000
−
| family             = Celeron
+
|locked=Yes
−
| series             = N3000
+
|frequency=1600 MHz
−
| locked             = Yes
+
|turbo frequency1=2480 MHz
−
| frequency           = 1600 MHz
+
|turbo frequency=Yes
−
| turbo frequency    = Yes
+
|bus type=IDI
−
| turbo frequency1    = 2480 MHz
+
|cpuid=406C4
−
| bus type           = IDI
+
|isa=x86-64
−
| bus speed          =  
+
|isa family=x86
−
| clock multiplier    =
+
|microarch=Airmont
−
| s-spec              = SR2KN
+
|core name=Braswell
−
| s-spec 2            =
+
|core stepping=D1
−
| s-spec es          =
+
|process=14 nm
−
| s-spec qs          = QK0J
+
|technology=CMOS
−
| cpuid              = 406C4
+
|word size=64 bit
−
 
+
|core count=2
−
| microarch           = Airmont
+
|thread count=2
−
| platform            =
+
|max cpus=1
−
| core name           = Braswell
+
|max memory=8 GiB
−
| core stepping       = D1
+
|sdp=4 W
−
| process             = 14 nm
+
|tdp=6 W
−
| transistors        =
+
|temp min=0 °C
−
| technology         = CMOS
+
|temp max=90 °C
−
| die size            =
+
|packaging=Yes
−
| word size           = 64 bit
+
|package=FCBGA1170
−
| core count         = 2
+
|package type=FCBGA
−
| thread count       = 2
+
|package size=25mm x 27mm x 1mm
−
| max cpus           = 1
+
|socket=BGA1170
−
| max memory         = 8 GB
+
|socket type=BGA
−
 
 
−
| electrical          = Yes
 
−
| sdp                 = 4 W
 
−
| tdp                 = 6 W
 
−
| temp max            = 90 °C
 
−
| temp min            = 0 °C
 
−
 
 
−
| packaging           = Yes
 
−
| package             = FCBGA1170
 
−
| package type       = FCBGA
 
−
| package size       = 25mm x 27mm x 1mm
 
−
| socket             = BGA1170
 
−
| socket type         = BGA
 
 
}}
 
}}
 
The '''{{intel|Celeron}} N3060''' is a {{arch|64}} dual-core [[system on a chip]] designed by Intel and introduced in early 2016. The N3060 is manufactured in [[14 nm process]] based on the {{intel|Airmont}} microarchitecture. This chip operates at 1.6 GHz with turbo mode of up to 2.48 GHz. This SoC incorporates the {{intel|HD Graphics 400}} GPU which has 12 execution units and operates at 320 MHz with up to 600 MHz bursts.
 
The '''{{intel|Celeron}} N3060''' is a {{arch|64}} dual-core [[system on a chip]] designed by Intel and introduced in early 2016. The N3060 is manufactured in [[14 nm process]] based on the {{intel|Airmont}} microarchitecture. This chip operates at 1.6 GHz with turbo mode of up to 2.48 GHz. This SoC incorporates the {{intel|HD Graphics 400}} GPU which has 12 execution units and operates at 320 MHz with up to 600 MHz bursts.
  
 
== Cache ==
 
== Cache ==
−
{{main|intel/microarchitectures/airmont#Memory_Hierarchy|l1=Airmont's Cache}}
+
{{main|intel/microarchitectures/airmont#Memory_Hierarchy|l1=Airmont § Cache}}
 
{{cache info
 
{{cache info
−
|l1i cache=64 KB
+
|l1i cache=64 KiB
−
|l1i break=2x32 KB
+
|l1i break=2x32 KiB
 
|l1i desc=8-way set associative
 
|l1i desc=8-way set associative
 
|l1i extra=(per core)
 
|l1i extra=(per core)
−
|l1d cache=48 KB
+
|l1d cache=48 KiB
−
|l1d break=2x24 KB
+
|l1d break=2x24 KiB
 
|l1d desc=6-way set associative
 
|l1d desc=6-way set associative
 
|l1d extra=(per core)
 
|l1d extra=(per core)
−
|l2 cache=1 MB
+
|l2 cache=1 MiB
−
|l2 break=1x1 MB
+
|l2 break=1x1 MiB
 
|l2 desc=16-way set associative
 
|l2 desc=16-way set associative
 
|l2 extra=(per 2 cores)
 
|l2 extra=(per 2 cores)
Line 96: Line 83:
 
| frequency          = 320 MHz
 
| frequency          = 320 MHz
 
| max frequency      = 600 MHz
 
| max frequency      = 600 MHz
−
| max memory          = 8 GB
+
| max memory          = 8 GiB
 
| output edp          = Yes
 
| output edp          = Yes
 
| output dp          = Yes
 
| output dp          = Yes
Line 135: Line 122:
  
 
== Expansions ==
 
== Expansions ==
−
{{mpu expansions
+
{{expansions
 
| pcie revision      = 2.0
 
| pcie revision      = 2.0
 
| pcie lanes        = 4
 
| pcie lanes        = 4
Line 149: Line 136:
  
 
== Features ==
 
== Features ==
−
{{mpu features
+
{{x86 features
−
| em64t    = Yes
+
|real=No
−
| nx        = Yes
+
|protected=No
−
| txt      =  
+
|smm=No
−
| tsx      =  
+
|fpu=No
−
| ht        =  
+
|x8616=No
−
| tbt2      =  
+
|x8632=No
−
| bpt      =  
+
|x8664=No
−
| vt-x      = Yes
+
|nx=Yes
−
| vt-d      =  
+
|mmx=Yes
−
| mmx      = Yes
+
|emmx=No
−
| sse       = Yes
+
|sse=Yes
−
| sse2     = Yes
+
|sse2=Yes
−
| sse3     = Yes
+
|sse3=Yes
−
| ssse3     = Yes
+
|ssse3=Yes
−
| sse4      = Yes
+
|sse41=Yes
−
| sse4.1    = Yes
+
|sse42=Yes
−
| sse4.2    = Yes
+
|sse4a=No
−
| aes       = Yes
+
|avx=No
−
| avx      =  
+
|avx2=No
−
| avx2      =  
+
|avx512f=No
−
| bmi      =  
+
|avx512cd=No
−
| bmi1      =  
+
|avx512er=No
−
| bmi2      =  
+
|avx512pf=No
−
| f16c     =  
+
|avx512bw=No
−
| fma3      =  
+
|avx512dq=No
−
| sgx       =  
+
|avx512vl=No
−
| eist      = Yes
+
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx512vnni=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|abm=No
 +
|tbm=No
 +
|bmi1=No
 +
|bmi2=No
 +
|fma3=No
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=No
 +
|sha=No
 +
|xop=No
 +
|adx=No
 +
|clmul=No
 +
|f16c=No
 +
|bfloat16=No
 +
|tbt1=No
 +
|tbt2=No
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=No
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=No
 +
|intelnodecontroller=No
 +
|intelnode=No
 +
|kpt=No
 +
|ptt=No
 +
|intelrunsure=No
 +
|mbe=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=No
 +
|txt=No
 +
|ht=No
 +
|vpro=No
 +
|vtx=Yes
 +
|vtd=No
 +
|ept=No
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|intqat=No
 +
|dlboost=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|amdpbod=No
 +
|em64t=Yes
 +
|vt-x=Yes
 +
|sse4=Yes
 +
|sse4_1=Yes
 +
|sse4_2=Yes
 
}}
 
}}
  

Latest revision as of 00:50, 24 November 2018

Edit Values
Intel Celeron N3060
General Info
DesignerIntel
ManufacturerIntel
Model NumberN3060
Part NumberFH8066501715929
S-SpecSR2KN
QK0J (QS)
MarketMobile
IntroductionJanuary 15, 2016 (announced)
January 15, 2016 (launched)
Release Price$107.00
ShopAmazon
General Specs
FamilyCeleron
SeriesN3000
LockedYes
Frequency1600 MHz
Turbo FrequencyYes
Turbo Frequency2480 MHz (1 core)
Bus typeIDI
CPUID406C4
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureAirmont
Core NameBraswell
Core SteppingD1
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores2
Threads2
Max Memory8 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
SDP4 W
TDP6 W
OP Temperature0 °C – 90 °C

The Celeron N3060 is a 64-bit dual-core system on a chip designed by Intel and introduced in early 2016. The N3060 is manufactured in 14 nm process based on the Airmont microarchitecture. This chip operates at 1.6 GHz with turbo mode of up to 2.48 GHz. This SoC incorporates the HD Graphics 400 GPU which has 12 execution units and operates at 320 MHz with up to 600 MHz bursts.

Cache[edit]

Main article: Airmont § Cache
Cache Info [Edit Values]
L1I$ 64 KiB
65,536 B
0.0625 MiB
2x32 KiB 8-way set associative (per core)
L1D$ 48 KiB
49,152 B
0.0469 MiB
2x24 KiB 6-way set associative (per core)
L2$ 1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
1x1 MiB 16-way set associative (per 2 cores)
L3$ 0 KiB
0 MiB
0 B
0 GiB
No L3$

Memory controller[edit]

Integrated Memory Controller
Type DDR3L-1600
Controllers 1
Channels 2
ECC Support No
Bandwidth (single) 12,800 MB/s
Bandwidth (dual) 25,600 MB/s
Max memory 8,192 MB

Graphics[edit]

Integrated Graphic Information
GPU HD Graphics 400
Execution Units 12
Displays 3
Frequency 320 MHz
0.32 GHz
320,000 KHz
Max frequency 600 MHz
0.6 GHz
600,000 KHz
Max memory 8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
Output DisplayPort, Embedded DisplayPort, HDMI
DirectX 11.1
OpenGL 4.2
OpenCL 1.2
DVI 1.4b
HDMI 1.4b
DVI 1.4b
DP 1.1a
eDP 1.4
Max HDMI Res 3840x2160 @30 Hz, 2560x1600 @60 Hz
Max DVI Res 3840x2160 @30 Hz, 2560x1600 @60 Hz
Max DP Res 3840x2160 @30 Hz, 2560x1600 @60 Hz
Max eDP Res 2560x1440 @60 Hz
  • Video decode hardware acceleration including support for H.263, MPEG4, H.264, H.265 (HEVC), VP8, VP9, MVC, MPEG2, VC1, JPEG.
  • Video encode hardware acceleration including support for H.264, H.263, VP8, MVC, JPEG.

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision2.0
Max Lanes4
Configs1x4, 1x2 + 2x1, 4x1
  • USB:
    • USB 3.0: 4 Super Speed (SS) Ports @ 5 Gb/s
    • USB 2.0: 1 High Speed (HS) + 4 Multiplexed with SS Ports @ 5 Gb/s
    • USB HSIC: 2 High Speed Ports @ 480 Mb/s

Features[edit]

Storage[edit]

  • SD Card Interface: v3.0
  • SDIO Interface: v3.0
  • eMMC Interface: v4.5.1
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/celeron/n3060&oldid=84401"
Facts about "Celeron N3060 - Intel"
RDF feed
has featureintegrated gpu +
integrated gpuHD Graphics 400 +
integrated gpu base frequency320 MHz (0.32 GHz, 320,000 KHz) +
integrated gpu max frequency600 MHz (0.6 GHz, 600,000 KHz) +
l1d$ description6-way set associative +
l1i$ description8-way set associative +
l2$ description16-way set associative +
l3$ descriptionNo L3$ +
l3$ size0 MiB (0 KiB, 0 B, 0 GiB) +