Difference between revisions of "intel/xeon e5/e5-4640 v4"

	Edit Values
	Xeon E5-4640 v4
	General Info
Designer	Intel
Manufacturer	Intel
Model Number	E5-4640 v4
Part Number	CM8066002061701
S-Spec	SR2SC; QKSS (QS)
Market	Server
Introduction	June 20, 2016 (announced); June 20, 2016 (launched)
Release Price	$2837
Shop	Amazon
	General Specs
Family	Xeon E5
Series	E5-4000
Locked	Yes
Frequency	2,100 MHz
Turbo Frequency	Yes
Turbo Frequency	2,600 MHz (1 core)
Bus type	QPI
Bus speed	4,000 MHz
Bus rate	2 × 8 GT/s
Clock multiplier	21
CPUID	406F1
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Broadwell
Platform	Grantley EP 4S
Chipset	C610 Series
Core Name	Broadwell EP
Core Family	6
Core Model	4F
Core Stepping	M0
Process	14 nm
Transistors	4,700,000,000
Technology	CMOS
Die	306.18 mm²
Word Size	64 bit
Cores	12
Threads	24
Max Memory	1,536 GiB
	Multiprocessing
Max SMP	4-Way (Multiprocessor)
	Electrical
Vcore	1.82 V
VI/O	1.2 V ± 3%
TDP	105 W
Tcase	0 °C – 80 °C
Tstorage	-25 °C – 125 °C

Latest revision as of 12:58, 13 November 2018

The Xeon E5-4640 v4 is a 64-bit dodeca-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for standard 4S environments. Operating at 2.1 GHz with a turbo boost frequency of 2.6 GHz for a single active core, this MPU has a TDP of 105 W and is manufactured on a 14 nm process (based on Broadwell).

Cache[edit]

Main article: Broadwell § Cache

Cache Info [Edit Values]
L1I$	384 KiB 393,216 B 0.375 MiB	12x32 KiB 8-way set associative (per core, write-back)
L1D$	384 KiB 393,216 B 0.375 MiB	12x32 KiB 8-way set associative (per core, write-back)
L2$	3 MiB 3,072 KiB 3,145,728 B 0.00293 GiB	12x256 KiB 8-way set associative (per core, write-back)
L3$	30 MiB 30,720 KiB 31,457,280 B 0.0293 GiB	12x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics[edit]

This microprocessor has no integrated graphics processing unit.

Memory controller[edit]

Integrated Memory Controller
Type	DDR4-2133
Controllers	1
Channels	4
ECC Support	Yes
Max bandwidth	63.58 GiB/s
Bandwidth (single)	15.89 GiB/s
Bandwidth (dual)	31.79 GiB/s
Max memory	1,536 GiB
Physical Address Extensions	46 bit

Expansions[edit]

[Edit/Modify Expansions Info]

Expansion Options

PCIe

Revision	3.0
Max Lanes	40
Configs	x4, x16

Features[edit]

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
F16C	16-bit Floating Point Conversion

NX	No-eXecute
HT	Hyper-Threading
TBT 2.0	Turbo Boost Technology 2.0
EIST	Enhanced SpeedStep Technology
TXT	Trusted Execution Technology (SMX)
EPT	Extended Page Tables (SLAT)
TSX	Transactional Synchronization Extensions

@@ Line 1: / Line 1: @@
 {{intel title|Xeon E5-4640 v4}}
-{{mpu
+{{chip
 | name                = Xeon E5-4640 v4
 | no image            = Yes
@@ Line 10: / Line 10: @@
 | model number        = E5-4640 v4
 | part number         = CM8066002061701
-| part number 1       =
 | part number 2       =
 | part number 3       =
+| part number 4       =
 | market              = Server
 | first announced     = June 20, 2016
@@ Line 34: / Line 34: @@
 | s-spec              = SR2SC
 | s-spec es           =
-| s-spec qs           =
+| s-spec qs           = QKSS
 | cpuid               = 406F1
+| isa family          = x86
+| isa                 = x86-64
 | microarch           = Broadwell
 | platform            = Grantley EP 4S
@@ Line 54: / Line 56: @@
 | max memory          = 1,536 GiB
-| electrical          = Yes
 | v core              = 1.82 V
 | v core tolerance    =
@@ Line 123: / Line 125: @@
 == Expansions ==
-{{mpu expansions
+{{expansions
 | pcie revision      = 3.0
 | pcie lanes         = 40
@@ Line 132: / Line 134: @@
 == Features ==
-{{mpu features
+{{x86 features
-| em64t       = Yes
+|real=No
-| nx          = Yes
+|protected=No
-| txt         = Yes
+|smm=No
-| tsx         = Yes
+|fpu=No
-| vpro        =
+|x8616=No
-| ht          = Yes
+|x8632=No
-| tbt1        =
+|x8664=No
-| tbt2        = Yes
+|nx=Yes
-| tbmt3       =
+|mmx=Yes
-| bpt         =
+|emmx=No
-| vt-x        = Yes
+|sse=Yes
-| vt-d        = Yes
+|sse2=Yes
-| ept         = Yes
+|sse3=Yes
-| mmx         = Yes
+|ssse3=Yes
-| sse         = Yes
+|sse41=No
-| sse2        = Yes
+|sse42=No
-| sse3        = Yes
+|sse4a=No
-| ssse3       = Yes
+|avx=Yes
-| sse4.1      = Yes
+|avx2=Yes
-| sse4.2      = Yes
+|avx512f=No
-| aes         = Yes
+|avx512cd=No
-| pclmul      = Yes
+|avx512er=No
-| avx         = Yes
+|avx512pf=No
-| avx2        = Yes
+|avx512bw=No
-| bmi         = Yes
+|avx512dq=No
-| bmi1        = Yes
+|avx512vl=No
-| bmi2        = Yes
+|avx512ifma=No
-| f16c        = Yes
+|avx512vbmi=No
-| fma3        = Yes
+|avx5124fmaps=No
-| mpx         =
+|avx5124vnniw=No
-| sgx         =
+|avx512vpopcntdq=No
-| eist        = Yes
+|abm=No
-| secure key  = Yes
+|tbm=No
-| os guard    = Yes
+|bmi1=Yes
-| intel at    =
+|bmi2=Yes
-| intel ipt   =
+|fma3=Yes
+|fma4=No
+|aes=Yes
+|rdrand=No
+|sha=No
+|xop=No
+|adx=No
+|clmul=No
+|f16c=Yes
+|tbt1=No
+|tbt2=Yes
+|tbmt3=No
+|bpt=No
+|eist=Yes
+|sst=No
+|flex=No
+|fastmem=No
+|ivmd=No
+|intelnodecontroller=No
+|intelnode=No
+|kpt=No
+|ptt=No
+|intelrunsure=No
+|mbe=No
+|isrt=No
+|sba=No
+|mwt=No
+|sipp=No
+|att=No
+|ipt=No
+|tsx=Yes
+|txt=Yes
+|ht=Yes
+|vpro=No
+|vtx=No
+|vtd=No
+|ept=Yes
+|mpx=No
+|sgx=No
+|securekey=No
+|osguard=No
+|intqat=No
+|3dnow=No
+|e3dnow=No
+|smartmp=No
+|powernow=No
+|amdvi=No
+|amdv=No
+|amdsme=No
+|amdtsme=No
+|amdsev=No
+|rvi=No
+|smt=No
+|sensemi=No
+|xfr=No
+|xfr2=No
+|mxfr=No
+|amdpb=No
+|amdpb2=No
+|amdpbod=No
+|em64t=Yes
+|vt-x=Yes
+|vt-d=Yes
+|sse4_1=Yes
+|sse4_2=Yes
+|pclmul=Yes
+|bmi=Yes
+|secure key=Yes
+|os guard=Yes
 }}

l1d$ description	8-way set associative +
l1d$ size	384 KiB (393,216 B, 0.375 MiB) +
l1i$ description	8-way set associative +
l1i$ size	384 KiB (393,216 B, 0.375 MiB) +
l2$ description	8-way set associative +
l2$ size	3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +
l3$ description	20-way set associative +
l3$ size	30 MiB (30,720 KiB, 31,457,280 B, 0.0293 GiB) +

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

MediaTek

NXP

Qualcomm

Renesas