From WikiChip
Difference between revisions of "intel/cores/kaby lake x"
(7 intermediate revisions by 3 users not shown) | |||
Line 3: | Line 3: | ||
|name=Kaby Lake X | |name=Kaby Lake X | ||
|image=kaby lake x (front).png | |image=kaby lake x (front).png | ||
− | |||
|image 2=kaby lake x (back).png | |image 2=kaby lake x (back).png | ||
− | |||
|developer=Intel | |developer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
Line 11: | Line 9: | ||
|first launched=June 26, 2017 | |first launched=June 26, 2017 | ||
|isa=x86-64 | |isa=x86-64 | ||
+ | |isa family=x86 | ||
|microarch=Kaby Lake | |microarch=Kaby Lake | ||
+ | |platform=Basin Falls | ||
|word=64 bit | |word=64 bit | ||
|proc=14 nm | |proc=14 nm | ||
|tech=CMOS | |tech=CMOS | ||
− | |clock min= | + | |clock min=4,000 MHz |
− | |clock max= | + | |clock max=4,300 MHz |
− | |package | + | |package name 1=intel,fclga_2066 |
|predecessor=Broadwell E | |predecessor=Broadwell E | ||
|predecessor link=intel/cores/broadwell e | |predecessor link=intel/cores/broadwell e | ||
− | |||
− | |||
|contemporary=Skylake X | |contemporary=Skylake X | ||
|contemporary link=intel/cores/skylake x | |contemporary link=intel/cores/skylake x | ||
Line 42: | Line 40: | ||
** Up to 64 GiB | ** Up to 64 GiB | ||
* Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2) | * Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2) | ||
− | * Support {{intel|Turbo Boost|Turbo Boost 2 | + | * Support {{intel|Turbo Boost|Turbo Boost 2.0}}, {{intel|VT-x}}, {{intel|VT-d}}, {{intel|SpeedStep}}, Software Guard ({{intel|SGX}}), and Memory Protection ({{intel|MPX}}) |
== Kaby Lake X Processors == | == Kaby Lake X Processors == | ||
Line 50: | Line 48: | ||
created and tagged accordingly. | created and tagged accordingly. | ||
− | Missing a chip? please dump its name here: | + | Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips |
--> | --> | ||
{{comp table start}} | {{comp table start}} | ||
− | <table class="comptable sortable | + | <table class="comptable sortable tc6 tc7"> |
− | + | {{comp table header|main|10:List of Kaby Lake X Processors}} | |
− | + | {{comp table header|cols|Family|Price|Launched|EOL|C|T|L3$|%TDP|Frequency|%Turbo}} | |
− | |||
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Kaby Lake X]] | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Kaby Lake X]] | ||
|?full page name | |?full page name | ||
|?model number | |?model number | ||
+ | |?microprocessor family | ||
+ | |?release price | ||
|?first launched | |?first launched | ||
− | |? | + | |?last order |
− | |||
|?core count | |?core count | ||
|?thread count | |?thread count | ||
Line 69: | Line 67: | ||
|?base frequency#GHz | |?base frequency#GHz | ||
|?turbo frequency (1 core)#GHz | |?turbo frequency (1 core)#GHz | ||
− | |||
|format=template | |format=template | ||
|template=proc table 3 | |template=proc table 3 | ||
Line 77: | Line 74: | ||
|userparam=12 | |userparam=12 | ||
|mainlabel=- | |mainlabel=- | ||
− | |||
}} | }} | ||
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Kaby Lake X]]}} | {{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Kaby Lake X]]}} |
Latest revision as of 09:07, 24 October 2018
Edit Values | |
Kaby Lake X | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Introduction | May 30, 2017 (announced) June 26, 2017 (launched) |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Kaby Lake |
Platform | Basin Falls |
Word Size | 8 octets 64 bit16 nibbles |
Process | 14 nm 0.014 μm 1.4e-5 mm |
Technology | CMOS |
Clock | 4,000 MHz - 4,300 MHz |
Packaging | |
Package | FCLGA-2066 (LGA) |
Dimension | 52.5 mm × 45 mm |
Pitch | 1.016 mm |
Contacts | 2066 |
Socket | Socket R4 |
Succession | |
Contemporary | |
Skylake X |
Kaby Lake X (KBL-X) is the name of the core for Intel's high-end desktop (HEDT) microprocessor line based on the Kaby Lake microarchitecture serving as a successor to Broadwell E and a contemporary to Skylake X. Kaby Lake X processors are fabricated on Intel's enhanced 14nm+ process and feature considerably higher base clock when compared to the the mainstream desktop series of Kaby Lake models.
Overview[edit]
Kaby Lake X based processors are a 2-chip solution - the microprocessor and the chipset. Kaby Lake X are Socket R4 and use the Lewisburg chipset (HUB).
Common Features[edit]
All Kaby Lake X processors have the following:
- TDP: 112 W
- Dual-channel Memory
- Up to DDR4-2666
- Up to 64 GiB
- Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2)
- Support Turbo Boost 2.0, VT-x, VT-d, SpeedStep, Software Guard (SGX), and Memory Protection (MPX)
Kaby Lake X Processors[edit]
List of Kaby Lake X Processors | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Model | Family | Price | Launched | EOL | C | T | L3$ | TDP | Frequency | Turbo |
i5-7640X | Core i5 | $ 242.00 € 217.80 £ 196.02 ¥ 25,005.86 | 26 June 2017 | 30 November 2018 | 4 | 4 | 6 MiB 6,144 KiB 6,291,456 B 0.00586 GiB | 112 W 112,000 mW 0.15 hp 0.112 kW | 4 GHz 4,000 MHz 4,000,000 kHz | 4.2 GHz 4,200 MHz 4,200,000 kHz |
i7-7740X | Core i7 | $ 339.00 € 305.10 £ 274.59 ¥ 35,028.87 | 26 June 2017 | 30 November 2018 | 4 | 8 | 8 MiB 8,192 KiB 8,388,608 B 0.00781 GiB | 112 W 112,000 mW 0.15 hp 0.112 kW | 4.3 GHz 4,300 MHz 4,300,000 kHz | 4.5 GHz 4,500 MHz 4,500,000 kHz |
Count: 2 |
See also[edit]
Facts about "Kaby Lake X - Cores - Intel"
designer | Intel + |
first announced | May 30, 2017 + |
first launched | June 26, 2017 + |
instance of | core + |
isa | x86-64 + |
isa family | x86 + |
main image | + and + |
manufacturer | Intel + |
microarchitecture | Kaby Lake + |
name | Kaby Lake X + |
package | FCLGA-2066 + |
platform | Basin Falls + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
socket | Socket R4 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |