From WikiChip
Difference between revisions of "pezy/pezy-1"
< pezy

(corrected misspell "peach" to peak)
 
(18 intermediate revisions by 4 users not shown)
Line 1: Line 1:
 
{{pezy title|PEZY-1}}
 
{{pezy title|PEZY-1}}
−
{{mpu
+
{{chip
−
| name               = PEZY-1
+
|name=PEZY-1
−
| no image           = Yes
+
|image=pezy 1.jpg
−
| image              =
+
|designer=PEZY
−
| image size          =
+
|manufacturer=TSMC
−
| caption            =  
+
|model number=PEZY-1
−
| designer           = PEZY
+
|market=Industrial
−
| manufacturer       = TSMC
+
|first announced=2011
−
| model number       = PEZY-1
+
|first launched=2012
−
| part number        =
+
|frequency=533.33 MHz
−
| market             = Industrial
+
|process=40 nm
−
| first announced     = 2011
+
|technology=CMOS
−
| first launched     = 2012
+
|die area=335 mm²
−
| last order          =
+
|die length=16.8 mm
−
| last shipment      =
+
|die width=21 mm
−
 
+
|core count=512
−
| family              =
+
|power=35 W
−
| series              =
+
|tjunc min=<!-- °C -->
−
| locked              =
+
|electrical=Yes
−
| frequency           = 533.33 MHz
+
|packaging=Yes
−
| bus type            =
+
|package 0=fcBGA-1517
−
| bus speed          = 66.66 MHz
+
|package 0 type=fcBGA
−
| bus rate            =
+
|package 0 pins=1517
−
| clock multiplier    = 8
+
|package 0 pitch=1 mm
−
 
+
|package 0 width=40 mm
−
| microarch          =
+
|package 0 length=40 mm
−
| platform            =
+
|package 0 height=3.01 mm
−
| chipset            =
+
|socket 0=BGA-1517
−
| core name          =
+
|socket 0 type=BGA
−
| core family        =
+
}}
−
| core model          =
+
'''PEZY-1''' was a first generation [[many-core microprocessor]] developed by [[PEZY]] in 2012. PEZY-1 contains 2 {{armh|ARM926}} cores ({{arm|ARMv5TEJ}}) along with 512 simpler RISC cores. Operating at 533 MHz, the processor is said to have peak performance of 533 GFLOPS (single-precision) and 266 GFLOPS (double-precision). PEZY-1 was designed using 220 million gates and manufactured on TSMC's [[40 nm process]].
−
| core stepping      =
 
−
| process             = 40 nm
 
−
| transistors        =
 
−
| technology         = CMOS
 
−
| die area           = 335 mm²
 
−
| die width          = 21 mm
 
−
| die length         = 16.8 mm
 
−
| word size          =  
 
−
| core count         = 512
 
−
| thread count        =  
 
−
| max cpus            =
 
−
| max memory          =  
 
−
| max memory addr    =
 
−
 
 
−
| electrical         = Yes
 
−
| power              = 35 W
 
−
| v core              =  
 
−
| v core tolerance    =  
 
−
| v io                =  
 
−
| v io tolerance      =  
 
−
| sdp                =  
 
−
| tdp                =  
 
−
| ctdp down          =  
 
−
| ctdp down frequency =  
 
−
| ctdp up            =  
 
−
| ctdp up frequency  =
 
−
| temp min            =
 
−
| temp max            =
 
−
| tjunc min          = <!-- °C -->
 
−
| tjunc max          =
 
−
| tcase min          =
 
−
| tcase max          =
 
−
| tstorage min        =
 
−
| tstorage max        =
 
  
−
| packaging          = Yes
+
The PEZY-1 is used for image processing devices and various medical instruments. In 2014 PEZY introduced their second generation many-core processor, the {{pezy|PEZY-SC}}, with twice as many cores and formed the basis for the {{pezy|PEZY-SCx}} family.
−
| package 0          = fcBGA-1517
 
−
| package 0 type      = fcBGA
 
−
| package 0 pins      = 1517
 
−
| package 0 pitch    = 1 mm
 
−
| package 0 width    = 40 mm
 
−
| package 0 length    = 40 mm
 
−
| package 0 height    = 3.01 mm
 
−
| socket 0            = BGA-1517
 
−
| socket 0 type      = BGA}}
 
−
'''PEZY-1''' was a first generation [[many-core microprocessor]] developed by [[PEZY]] in 2012. PEZY-1 contains 2 {{armh|ARM926}} cores ({{arm|ARMv5TEJ}}) along with 512 simpler RISC cores. Operating at 533 MHz, the processor is said to have peach performance of 533 GFLOPS (single-precision) and 266 GFLOPS (double-precision). PEZY-1 was designed using 220 million gates and manufactured on TSMC's [[40 nm process]].
 
−
 
 
−
The PEZY-1 is used for image processing devices and various medical instruments.
 
  
 
== Cache ==
 
== Cache ==
−
PEZY-1's cache is seperate from the {{armh|ARM926}}'s cache which has an L1$ of 16KB (2x) and no L2$.
+
PEZY-1's cache is separate from the {{armh|ARM926}}'s cache which has an L1$ of 16 KiB (2x) and no L2$.
−
{{cache info
+
{{cache size
−
|l1 cache=128 KB
+
|l1 cache=128 KiB
−
|l1 break=
+
|l1i cache=64 KiB
−
|l1 desc=
+
|l1i break=1x64 KiB
−
|l1 extra=
+
|l1d cache=64 KiB
−
|l2 cache=1 MB
+
|l1d break=1x64 KiB
−
|l2 break=
+
|l2 cache=1 MiB
−
|l2 desc=
+
|l2 break=1x1 MiB
−
|l2 extra=
 
−
|l3 cache=0 KB
 
−
|l3 desc=No L3$
 
 
}}
 
}}
  
 
== Memory controller ==
 
== Memory controller ==
−
{{integrated memory controller
+
{{memory controller
−
| type               = DDR3-1333
+
|type=DDR3-1333
−
| controllers       = 1
+
|ecc=Yes
−
| channels           = 4
+
|controllers=4
−
| ecc support        = <!-- ?? -->
+
|channels=4
−
| bandwidth schan    = 10,666 MB/s
+
|width=64 bit
−
| bandwidth dchan    = 21,333 MB/s
+
|max bandwidth=39.74 GiB/s
−
| bandwidth qchan    = 42,666 MB/s
+
|bandwidth schan=9.93 GiB/s
−
| max memory        = 64 GB
+
|bandwidth dchan=19.86 GiB/s
 +
|bandwidth qchan=39.74 GiB/
 
}}
 
}}
  
 
== Expansions ==
 
== Expansions ==
−
{{mpu expansions
+
{{expansions
 
| pcie revision      = 2.0
 
| pcie revision      = 2.0
−
| pcie lanes        = 4
+
| pcie lanes        = 24
−
| pcie config        =  
+
| pcie config        = 6x4
−
| pcie config 1      =
+
| uart              = Yes
−
| pcie config 2      =
+
| gp io              = Yes
−
| usb revision      =
 
−
| usb revision 2    =
 
−
| usb ports          =
 
−
| sata revision      =
 
−
| sata ports        =
 
−
| integrated lan    =
 
−
| uart              =  
 
−
| gp io              =  
 
 
}}
 
}}
  
 
== PEZY-1 Quad PCI Board ==
 
== PEZY-1 Quad PCI Board ==
 
[[File:pezy 1 quad pci board.jpg|200px|right]]
 
[[File:pezy 1 quad pci board.jpg|200px|right]]
−
PEZY has developed a Quad-PEZY-1 PCI board for their microprocessors which has 4 PEZY-1 for a total of 2,048 PE cores (along with 8 ARM cores). The board is equipped with 64 GB of memory for a total bandwidth of 200 GB/s. PEZY reports the total computational power for the board to be at 2.56 TFLOPS with a power consumption of 180 Watts.
+
PEZY has developed a Quad-PEZY-1 PCI board for their microprocessors which has 4 PEZY-1 for a total of 2,048 PE cores (along with 8 ARM cores). The board is equipped with 64 GiB of memory for a total bandwidth of 200 GB/s. PEZY reports the total computational power for the board to be at 2.56 TFLOPS with a power consumption of 180 Watts.
 +
 
 +
== Documents ==
 +
* [[:File:pezy 1 board.pdf|PEZY-1 Board]]
 +
* [[:File:PEZY Computing (February 20, 2015).pdf|PEZY Computing (February 20, 2015)]]

Latest revision as of 02:48, 20 October 2018

Edit Values
PEZY-1
pezy 1.jpg
General Info
DesignerPEZY
ManufacturerTSMC
Model NumberPEZY-1
MarketIndustrial
Introduction2011 (announced)
2012 (launched)
General Specs
Frequency533.33 MHz
Microarchitecture
Process40 nm
TechnologyCMOS
Die335 mm²
16.8 mm × 21 mm
Cores512
Electrical
Power dissipation35 W

PEZY-1 was a first generation many-core microprocessor developed by PEZY in 2012. PEZY-1 contains 2 ARM926 cores (ARMv5TEJ) along with 512 simpler RISC cores. Operating at 533 MHz, the processor is said to have peak performance of 533 GFLOPS (single-precision) and 266 GFLOPS (double-precision). PEZY-1 was designed using 220 million gates and manufactured on TSMC's 40 nm process.

The PEZY-1 is used for image processing devices and various medical instruments. In 2014 PEZY introduced their second generation many-core processor, the PEZY-SC, with twice as many cores and formed the basis for the PEZY-SCx family.

Cache[edit]

PEZY-1's cache is separate from the ARM926's cache which has an L1$ of 16 KiB (2x) and no L2$.

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
1x64 KiB  
L1D$64 KiB
65,536 B
0.0625 MiB
1x64 KiB  
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  1x1 MiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1333
Supports ECCYes
Controllers4
Channels4
Width64 bit
Max Bandwidth39.74 GiB/s
40,693.76 MiB/s
42.671 GB/s
42,670.5 MB/s
0.0388 TiB/s
0.0427 TB/s
Bandwidth
Single 9.93 GiB/s
Double 19.86 GiB/s
Quad 39.74 GiB/

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision2.0
Max Lanes24
Configs6x4
UART
GP I/OYes


PEZY-1 Quad PCI Board[edit]

pezy 1 quad pci board.jpg

PEZY has developed a Quad-PEZY-1 PCI board for their microprocessors which has 4 PEZY-1 for a total of 2,048 PE cores (along with 8 ARM cores). The board is equipped with 64 GiB of memory for a total bandwidth of 200 GB/s. PEZY reports the total computational power for the board to be at 2.56 TFLOPS with a power consumption of 180 Watts.

Documents[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=pezy/pezy-1&oldid=83408"
Facts about "PEZY-1 - PEZY"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
PEZY-1 - PEZY#io +
base frequency533.33 MHz (0.533 GHz, 533,330 kHz) +
core count512 +
designerPEZY +
die area335 mm² (0.519 in², 3.35 cm², 335,000,000 µm²) +
die length16.8 mm (1.68 cm, 0.661 in, 16,800 µm) +
die width21 mm (2.1 cm, 0.827 in, 21,000 µm) +
first announced2011 +
first launched2012 +
full page namepezy/pezy-1 +
has ecc memory supporttrue +
instance ofmicroprocessor +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldate2012 +
main imageFile:pezy 1.jpg +
manufacturerTSMC +
market segmentIndustrial +
max memory bandwidth39.74 GiB/s (40,693.76 MiB/s, 42.671 GB/s, 42,670.5 MB/s, 0.0388 TiB/s, 0.0427 TB/s) +
max memory channels4 +
max pcie lanes24 +
model numberPEZY-1 +
namePEZY-1 +
power dissipation35 W (35,000 mW, 0.0469 hp, 0.035 kW) +
process40 nm (0.04 μm, 4.0e-5 mm) +
supported memory typeDDR3-1333 +
technologyCMOS +