Semiconductor & Computer Engineering
(→Overview) |
(→Overview) |
||
| Line 7: | Line 7: | ||
=== AArch32 === | === AArch32 === | ||
{{main|arm/aarch32|l1=AArch32}} | {{main|arm/aarch32|l1=AArch32}} | ||
| − | ARMv8 introduced the concept of {{\\|AArch32}} execution state to incorporate what was | + | ARMv8 introduced the concept of {{\\|AArch32}} execution state to incorporate what was previously {{\\|ARMv7}}. It covers the {{\\|A32}} and {{\\|T32}} instruction sets along with a number of new instructions. AArch32 keeps the classical ARM exception model and limits the virtual address to 32 bits. |
=== AArch64 === | === AArch64 === | ||
Revision as of 15:34, 20 September 2018
| ARM ISA | |
| General | |
| Variants | |
| Extensions | |
| Topics | |
| Versions(all) | |
ARMv8 is the successor to ARMv7, an ARM instruction set architecture announced in 2011 which brought a large number of fundumental changes to the instruction set, including the introduction of 64-bit operating capabilities.
Overview
Work on the ARMv8 started within the R&D group at ARM in 2007. First disclosed in late 2011, the ARMv8 is a successor and an extension to the ARMv7 ISA. This architecture introduced new 64-bit operating capabilities, called AArch64, and defined a relationship to the prior 32-bit operating state, referred to as AArch32 (covering the A32 and T32 ISAs). Foundationally, ARMv8 extends the old architecture while maintaining compatibility with older revisions and extensions (e.g., Thumb, NEON, VFP) when in AArch32. Additionally, ARMv8 introduced a number of enhancements to AArch32 which still maintains full compatibility with ARMv7. Generally speaking, ARMv8 was designed such that a well-designed AArch64 core should also work well as an AArch32 core.
AArch32
- Main article: AArch32
ARMv8 introduced the concept of AArch32 execution state to incorporate what was previously ARMv7. It covers the A32 and T32 instruction sets along with a number of new instructions. AArch32 keeps the classical ARM exception model and limits the virtual address to 32 bits.
AArch64
- Main article: AArch64
ARMv8 introduced the new AArch64 execution state that operates on a new instruction set called the A64. This mode reworked the exception handling model in ARM, making it simpler with fewer modes and banked registers. With 64-bit support, up to 48 bits of virtual address was introduced (note that it's actually an extension of the Large Physical Address Extension which was introduced in ARMv7 but was developed concurrently with the ARMv8). Additionally, both security (TrustZone) and virtualization carries over to AArch64.
Profiles
ARMv8 introduced a number of profiles or flavor of the architecture that targets certain classes of workloads.
| Profile | Name | Description |
|---|---|---|
| Application | ARMv8-A | Optimized for a large class of general applications for mobile, tablets, and servers. |
| Real-Time | ARMv8-R | Optimized for safety-critical environments. |
| Microcontroller | ARMv8-M | Optimized for embedded systems with a highly deterministic operation. |
Crypto Extension
ARMv8 introduced hardware acceleration for cryptography. Those operations were added to complement, but not replace, traditional crypto accelerators. Geared for small instruction-level crypto support, two main algorithms were supported: AES and SHA (SHA-1 and SHA-256).
Bibliography
- Richard Grisenthwaite. (October 26, 2011). "Technology Preview: The ARM Architecture - a View of the Future ".
- ARM Architecture Group. "Armv8 instruction set overview." vol. PRD03-GENC-010197 (2011).