Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/microarchitectures/sapphire rapids"
(→Key changes from {{\\|Ice Lake (server)|Ice Lake}}) |
|||
| Line 20: | Line 20: | ||
== Architecture == | == Architecture == | ||
| + | {{future information}} | ||
=== Key changes from {{\\|Ice Lake (server)|Ice Lake}}=== | === Key changes from {{\\|Ice Lake (server)|Ice Lake}}=== | ||
| − | {{ | + | * Platform |
| + | ** {{intel|Whitley|l=platform}} '''→''' {{intel|Tinsley|l=platform}} | ||
Revision as of 23:52, 13 April 2018
| Edit Values | |
| Sapphire Rapids µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2020 |
| Process | 10 nm |
| Instructions | |
| ISA | x86-64 |
| Succession | |
Sapphire Rapids (SPR) is Intel's successor to Ice Lake, a 10 nm microarchitecture for for enthusiasts and servers.
Process Technology
Sapphire Rapids is planned to be manufactured on Intel's 3rd generation enhanced 10nm++ process.
Architecture
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
Key changes from Ice Lake
Facts about "Sapphire Rapids - Microarchitectures - Intel"
| codename | Sapphire Rapids + |
| designer | Intel + |
| first launched | 2020 + |
| full page name | intel/microarchitectures/sapphire rapids + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Sapphire Rapids + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |