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Difference between revisions of "intel/xeon e3/e3-1240 v5"
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| − | {{intel title|Xeon E3-1240 | + | {{intel title|Xeon E3-1240 v5}} |
| − | {{ | + | {{chip |
| − | | name | + | |name=Xeon E3-1240 v5 |
| − | | | + | |image=skylake dt (front).png |
| − | + | |designer=Intel | |
| − | + | |manufacturer=Intel | |
| − | + | |model number=E3-1240 v5 | |
| − | | designer | + | |part number=CM8066201921715 |
| − | | manufacturer | + | |part number 2=BX80662E31240V5 |
| − | | model number | + | |s-spec=SR2CM |
| − | | part number | + | |s-spec 2=SR2LD |
| − | | part number 2 | + | |market=Server |
| − | | market | + | |first announced=October 19, 2015 |
| − | | first announced | + | |first launched=October 19, 2015 |
| − | | first launched | + | |last order=October 26, 2018 |
| − | | last order | + | |last shipment=April 12, 2019 |
| − | | last shipment | + | |release price=$282 |
| − | + | |family=Xeon E3 | |
| − | | family | + | |series=E3-1200 v5 |
| − | | series | + | |locked=Yes |
| − | | locked | + | |frequency=3,500 MHz |
| − | | frequency | + | |turbo frequency1=3,900 MHz |
| − | + | |turbo frequency=Yes | |
| − | | turbo frequency1 | + | |bus type=DMI 3.0 |
| − | | turbo | + | |bus links=4 |
| − | + | |bus rate=8 GT/s | |
| − | + | |clock multiplier=35 | |
| − | | bus type | + | |cpuid=506E3 |
| − | | bus | + | |isa=x86-64 |
| − | | bus rate | + | |isa family=x86 |
| − | | clock multiplier | + | |microarch=Skylake |
| − | | | + | |platform=Greenlow |
| − | | | + | |chipset=Sunrise Point |
| − | + | |core name=Skylake DT | |
| − | | | + | |core family=6 |
| − | + | |core model=94 | |
| − | + | |core stepping=R0 | |
| − | | microarch | + | |process=14 nm |
| − | | platform | + | |technology=CMOS |
| − | | chipset | + | |die area=122 mm² |
| − | | core name | + | |word size=64 bit |
| − | | core family | + | |core count=4 |
| − | | core model | + | |thread count=8 |
| − | | core stepping | + | |max cpus=1 |
| − | | process | + | |max memory=64 GiB |
| − | + | |v core min=0.55 V | |
| − | | technology | + | |v core max=1.52 V |
| − | | die | + | |tdp=80 W |
| − | | word size | + | |tjunc min=0 °C |
| − | | core count | + | |tjunc max=100 °C |
| − | | thread count | + | |tstorage min=-25 °C |
| − | | max cpus | + | |tstorage max=125 °C |
| − | | max memory | + | |package module 1={{packages/intel/lga-1151}} |
| − | |||
| − | |||
| − | | v core | ||
| − | | v core | ||
| − | |||
| − | | tdp | ||
| − | | | ||
| − | |||
| − | |||
| − | | | ||
| − | |||
| − | | | ||
| − | |||
| − | | | ||
| − | | package | ||
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}} | }} | ||
| − | + | '''Xeon E3-1240 v5''' is an entry-level server and workstation {{arch|64}} [[quad-core]] [[x86]] microprocessor introduced by [[Intel]] in October 2015. This {{intel|Skylake}}-based chip operates at 3.5 GHz with turbo boost of 3.9 GHz. The E3-1240 V5 has a TDP of 80 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has no [[integrated graphics processor]]. | |
== Cache == | == Cache == | ||
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} | {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} | ||
| − | {{cache | + | {{cache size |
| + | |l1 cache=256 KiB | ||
|l1i cache=128 KiB | |l1i cache=128 KiB | ||
|l1i break=4x32 KiB | |l1i break=4x32 KiB | ||
|l1i desc=8-way set associative | |l1i desc=8-way set associative | ||
| − | |||
|l1d cache=128 KiB | |l1d cache=128 KiB | ||
|l1d break=4x32 KiB | |l1d break=4x32 KiB | ||
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
| − | |l1d | + | |l1d policy=write-back |
|l2 cache=1 MiB | |l2 cache=1 MiB | ||
|l2 break=4x256 KiB | |l2 break=4x256 KiB | ||
|l2 desc=4-way set associative | |l2 desc=4-way set associative | ||
| − | |l2 | + | |l2 policy=write-back |
|l3 cache=8 MiB | |l3 cache=8 MiB | ||
|l3 break=4x2 MiB | |l3 break=4x2 MiB | ||
| + | |l3 policy=write-back | ||
}} | }} | ||
| − | |||
| − | |||
| − | |||
== Memory controller == | == Memory controller == | ||
| − | {{ | + | {{memory controller |
| − | | type | + | |type=DDR3L-1600 |
| − | | type 2 | + | |type 2=DDR4-2133 |
| − | + | |ecc=Yes | |
| − | + | |max mem=64 GiB | |
| − | + | |controllers=1 | |
| − | + | |channels=2 | |
| − | | | + | |max bandwidth=31.79 GiB/s |
| − | | | + | |bandwidth schan=15.89 GiB/s |
| − | | controllers | + | |bandwidth dchan=31.79 GiB/s |
| − | | channels | ||
| − | |||
| − | | max bandwidth | ||
| − | | bandwidth schan | ||
| − | | bandwidth dchan | ||
| − | |||
}} | }} | ||
== Expansions == | == Expansions == | ||
| − | {{ | + | {{expansions |
| pcie revision = 3.0 | | pcie revision = 3.0 | ||
| pcie lanes = 16 | | pcie lanes = 16 | ||
| pcie config = 1x16 | | pcie config = 1x16 | ||
| − | | pcie config | + | | pcie config 2 = 2x8 |
| − | | pcie config | + | | pcie config 3 = 1x8+2x4 |
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
}} | }} | ||
| − | == Features == | + | == Graphics == |
| − | {{ | + | This chip has no integrated graphics processing unit. |
| − | | | + | |
| − | | nx | + | == Features == |
| − | | | + | {{x86 features |
| − | | | + | |real=Yes |
| − | | | + | |protected=Yes |
| − | | | + | |smm=Yes |
| − | | | + | |fpu=Yes |
| − | | | + | |x8616=Yes |
| − | | | + | |x8632=Yes |
| − | | | + | |x8664=Yes |
| − | | | + | |nx=Yes |
| − | | | + | |mmx=Yes |
| − | | | + | |emmx=Yes |
| − | | | + | |sse=Yes |
| − | | | + | |sse2=Yes |
| − | | | + | |sse3=Yes |
| − | | | + | |ssse3=Yes |
| − | | | + | |sse41=Yes |
| − | | | + | |sse42=Yes |
| − | | | + | |sse4a=No |
| − | | | + | |avx=Yes |
| − | | | + | |avx2=Yes |
| − | | | + | |
| − | | | + | |abm=Yes |
| − | | | + | |tbm=No |
| − | | | + | |bmi1=Yes |
| − | | | + | |bmi2=Yes |
| − | | | + | |fma3=Yes |
| − | | | + | |fma4=No |
| − | | mpx | + | |aes=Yes |
| − | | sgx | + | |rdrand=Yes |
| − | | | + | |sha=No |
| − | | | + | |xop=No |
| − | | | + | |adx=Yes |
| + | |clmul=Yes | ||
| + | |f16c=Yes | ||
| + | |tbt1=No | ||
| + | |tbt2=Yes | ||
| + | |tbmt3=No | ||
| + | |bpt=No | ||
| + | |eist=Yes | ||
| + | |sst=No | ||
| + | |flex=No | ||
| + | |fastmem=No | ||
| + | |isrt=No | ||
| + | |sba=No | ||
| + | |mwt=No | ||
| + | |sipp=No | ||
| + | |att=No | ||
| + | |ipt=No | ||
| + | |tsx=Yes | ||
| + | |txt=Yes | ||
| + | |ht=Yes | ||
| + | |vpro=Yes | ||
| + | |vtx=Yes | ||
| + | |vtd=Yes | ||
| + | |ept=Yes | ||
| + | |mpx=Yes | ||
| + | |sgx=Yes | ||
| + | |securekey=Yes | ||
| + | |osguard=Yes | ||
| + | |3dnow=No | ||
| + | |e3dnow=No | ||
| + | |smartmp=No | ||
| + | |powernow=No | ||
| + | |amdvi=No | ||
| + | |amdv=No | ||
| + | |amdsme=No | ||
| + | |amdtsme=No | ||
| + | |amdsev=No | ||
| + | |rvi=No | ||
| + | |smt=No | ||
| + | |sensemi=No | ||
| + | |xfr=No | ||
}} | }} | ||
Latest revision as of 23:29, 6 April 2018
| Edit Values | ||||||||||||
| Xeon E3-1240 v5 | ||||||||||||
 | ||||||||||||
| General Info | ||||||||||||
| Designer | Intel | |||||||||||
| Manufacturer | Intel | |||||||||||
| Model Number | E3-1240 v5 | |||||||||||
| Part Number | CM8066201921715, BX80662E31240V5 | |||||||||||
| S-Spec | SR2CM, SR2LD | |||||||||||
| Market | Server | |||||||||||
| Introduction | October 19, 2015 (announced) October 19, 2015 (launched) | |||||||||||
| End-of-life | October 26, 2018 (last order) April 12, 2019 (last shipment) | |||||||||||
| Release Price | $282 | |||||||||||
| Shop | Amazon | |||||||||||
| General Specs | ||||||||||||
| Family | Xeon E3 | |||||||||||
| Series | E3-1200 v5 | |||||||||||
| Locked | Yes | |||||||||||
| Frequency | 3,500 MHz | |||||||||||
| Turbo Frequency | Yes | |||||||||||
| Turbo Frequency | 3,900 MHz (1 core) | |||||||||||
| Bus type | DMI 3.0 | |||||||||||
| Bus rate | 4 × 8 GT/s | |||||||||||
| Clock multiplier | 35 | |||||||||||
| CPUID | 506E3 | |||||||||||
| Microarchitecture | ||||||||||||
| ISA | x86-64 (x86) | |||||||||||
| Microarchitecture | Skylake | |||||||||||
| Platform | Greenlow | |||||||||||
| Chipset | Sunrise Point | |||||||||||
| Core Name | Skylake DT | |||||||||||
| Core Family | 6 | |||||||||||
| Core Model | 94 | |||||||||||
| Core Stepping | R0 | |||||||||||
| Process | 14 nm | |||||||||||
| Technology | CMOS | |||||||||||
| Die | 122 mm² | |||||||||||
| Word Size | 64 bit | |||||||||||
| Cores | 4 | |||||||||||
| Threads | 8 | |||||||||||
| Max Memory | 64 GiB | |||||||||||
| Multiprocessing | ||||||||||||
| Max SMP | 1-Way (Uniprocessor) | |||||||||||
| Electrical | ||||||||||||
| Vcore | 0.55 V-1.52 V | |||||||||||
| TDP | 80 W | |||||||||||
| Tjunction | 0 °C – 100 °C | |||||||||||
| Tstorage | -25 °C – 125 °C | |||||||||||
| Packaging | ||||||||||||
| ||||||||||||
Xeon E3-1240 v5 is an entry-level server and workstation 64-bit quad-core x86 microprocessor introduced by Intel in October 2015. This Skylake-based chip operates at 3.5 GHz with turbo boost of 3.9 GHz. The E3-1240 V5 has a TDP of 80 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has no integrated graphics processor.
Cache[edit]
- Main article: Skylake § Cache
 |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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Graphics[edit]
This chip has no integrated graphics processing unit.
Features[edit]
[Edit/Modify Supported Features]
Facts about "Xeon E3-1240 v5 - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon E3-1240 v5 - Intel#package + and Xeon E3-1240 v5 - Intel#io + |
| base frequency | 3,500 MHz (3.5 GHz, 3,500,000 kHz) + |
| bus links | 4 + |
| bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
| bus type | DMI 3.0 + |
| chipset | Sunrise Point + |
| clock multiplier | 35 + |
| core count | 4 + |
| core family | 6 + |
| core model | 94 + |
| core name | Skylake DT + |
| core stepping | R0 + |
| core voltage (max) | 1.52 V (15.2 dV, 152 cV, 1,520 mV) + |
| core voltage (min) | 0.55 V (5.5 dV, 55 cV, 550 mV) + |
| cpuid | 506E3 + |
| designer | Intel + |
| die area | 122 mm² (0.189 in², 1.22 cm², 122,000,000 µm²) + |
| family | Xeon E3 + |
| first announced | October 19, 2015 + |
| first launched | October 19, 2015 + |
| full page name | intel/xeon e3/e3-1240 v5 + |
| has advanced vector extensions | true + |
| has advanced vector extensions 2 | true + |
| has ecc memory support | true + |
| has extended page tables support | true + |
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology + and OS Guard + |
| has intel enhanced speedstep technology | true + |
| has intel secure key technology | true + |
| has intel supervisor mode execution protection | true + |
| has intel trusted execution technology | true + |
| has intel turbo boost technology 2 0 | true + |
| has intel vpro technology | true + |
| has intel vt-d technology | true + |
| has intel vt-x technology | true + |
| has locked clock multiplier | true + |
| has second level address translation support | true + |
| has simultaneous multithreading | true + |
| has transactional synchronization extensions | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| instance of | microprocessor + |
| isa | x86-64 + |
| isa family | x86 + |
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
| last order | October 26, 2018 + |
| last shipment | April 12, 2019 + |
| ldate | October 19, 2015 + |
| main image | .png) + |
| manufacturer | Intel + |
| market segment | Server + |
| max cpu count | 1 + |
| max junction temperature | 373.15 K (100 °C, 212 °F, 671.67 °R) + |
| max memory | 65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) + |
| max memory bandwidth | 31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
| max memory channels | 2 + |
| max pcie lanes | 16 + |
| max storage temperature | 398.15 K (125 °C, 257 °F, 716.67 °R) + |
| microarchitecture | Skylake + |
| min junction temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
| min storage temperature | 248.15 K (-25 °C, -13 °F, 446.67 °R) + |
| model number | E3-1240 v5 + |
| name | Xeon E3-1240 v5 + |
| package | FCLGA-1151 + |
| part number | CM8066201921715 + and BX80662E31240V5 + |
| platform | Greenlow + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |
| release price | $ 282.00 (€ 253.80, £ 228.42, ¥ 29,139.06) + |
| s-spec | SR2CM + and SR2LD + |
| series | E3-1200 v5 + |
| smp max ways | 1 + |
| socket | LGA-1151 + |
| supported memory type | DDR3L-1600 + and DDR4-2133 + |
| tdp | 80 W (80,000 mW, 0.107 hp, 0.08 kW) + |
| technology | CMOS + |
| thread count | 8 + |
| turbo frequency (1 core) | 3,900 MHz (3.9 GHz, 3,900,000 kHz) + |
| word size | 64 bit (8 octets, 16 nibbles) + |
| x86/has memory protection extensions | true + |
| x86/has software guard extensions | true + |
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