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Difference between revisions of "intel/xeon e3/e3-1220 v5"
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| − | {{intel title|Xeon E3-1220 | + | {{intel title|Xeon E3-1220 v5}} |
| − | {{ | + | {{chip |
| − | | name | + | |name=Xeon E3-1220 v5 |
| − | | | + | |image=skylake dt (front).png |
| − | + | |designer=Intel | |
| − | + | |manufacturer=Intel | |
| − | + | |model number=E3-1220 v5 | |
| − | | designer | + | |part number=CM8066201921804 |
| − | | manufacturer | + | |part number 2=BX80662E31220V5 |
| − | | model number | + | |s-spec=SR2CQ |
| − | | part number | + | |s-spec 2=SR2LG |
| − | | part number 2 | + | |market=Server |
| − | | market | + | |first announced=October 19, 2015 |
| − | | first announced | + | |first launched=October 19, 2015 |
| − | | first launched | + | |last order=October 26, 2018 |
| − | | last order | + | |last shipment=April 12, 2019 |
| − | | last shipment | + | |release price=$203.00 |
| − | | release price | + | |family=Xeon E3 |
| − | + | |series=E3-1200 v5 | |
| − | | family | + | |locked=Yes |
| − | | series | + | |frequency=3,000 MHz |
| − | | locked | + | |turbo frequency1=3,500 MHz |
| − | | frequency | + | |turbo frequency=Yes |
| − | + | |bus type=DMI 3.0 | |
| − | | turbo frequency1 | + | |bus links=4 |
| − | | turbo | + | |bus rate=8 GT/s |
| − | + | |clock multiplier=30 | |
| − | + | |cpuid=506E3 | |
| − | | bus type | + | |isa=x86-64 |
| − | | bus | + | |isa family=x86 |
| − | | bus rate | + | |microarch=Skylake |
| − | | clock multiplier | + | |platform=Greenlow |
| − | + | |chipset=Sunrise Point | |
| − | + | |core name=Skylake DT | |
| − | + | |core family=6 | |
| − | + | |core model=94 | |
| − | | cpuid | + | |core stepping=R0 |
| − | + | |process=14 nm | |
| − | | isa | + | |technology=CMOS |
| − | | isa | + | |die area=122 mm² |
| − | | microarch | + | |word size=64 bit |
| − | | platform | + | |core count=4 |
| − | | chipset | + | |thread count=4 |
| − | | core name | + | |max cpus=1 |
| − | | core family | + | |max memory=64 GiB |
| − | | core model | + | |v core min=0.55 V |
| − | | core stepping | + | |v core max=1.52 V |
| − | | process | + | |tdp=80 W |
| − | + | |tjunc min=0 °C | |
| − | | technology | + | |tjunc max=100 °C |
| − | | die area | + | |tstorage min=-25 °C |
| − | | word size | + | |tstorage max=125 °C |
| − | | core count | + | |package module 1={{packages/intel/lga-1151}} |
| − | | thread count | ||
| − | | max cpus | ||
| − | | max memory | ||
| − | |||
| − | |||
| − | | v core | ||
| − | | v core | ||
| − | |||
| − | | tdp | ||
| − | | tjunc min | ||
| − | | tjunc max | ||
| − | |||
| − | |||
| − | | tstorage min | ||
| − | | tstorage max | ||
| − | |||
| − | |||
| − | |||
| − | | package module 1 | ||
}} | }} | ||
| − | '''Xeon E3-1220 | + | '''Xeon E3-1220 v5''' is an entry-level server and workstation {{arch|64}} [[quad-core]] [[x86]] microprocessor introduced by [[Intel]] in October 2015. This {{intel|Skylake}}-based chip operates at 3 GHz with turbo boost of 3.5 GHz. The E3-1220 v5 has a [[TDP]] of 80 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has no [[integrated graphics processor]]. |
== Cache == | == Cache == | ||
| Line 91: | Line 72: | ||
|l3 cache=8 MiB | |l3 cache=8 MiB | ||
|l3 break=4x2 MiB | |l3 break=4x2 MiB | ||
| − | |||
|l3 policy=write-back | |l3 policy=write-back | ||
}} | }} | ||
| Line 97: | Line 77: | ||
== Memory controller == | == Memory controller == | ||
{{memory controller | {{memory controller | ||
| − | |type=DDR3L-1600 | + | |type=DDR3L-1600 |
|type 2=DDR4-2133 | |type 2=DDR4-2133 | ||
|ecc=Yes | |ecc=Yes | ||
| Line 103: | Line 83: | ||
|controllers=1 | |controllers=1 | ||
|channels=2 | |channels=2 | ||
| − | |max bandwidth= | + | |max bandwidth=31.79 GiB/s |
| − | |bandwidth schan= | + | |bandwidth schan=15.89 GiB/s |
| − | |bandwidth dchan= | + | |bandwidth dchan=31.79 GiB/s |
}} | }} | ||
| Line 120: | Line 100: | ||
This chip has no integrated graphics processing unit. | This chip has no integrated graphics processing unit. | ||
| − | == Features == | + | == Features == |
| − | {{ | + | {{x86 features |
| − | | | + | |real=Yes |
| − | | nx | + | |protected=Yes |
| − | | | + | |smm=Yes |
| − | | | + | |fpu=Yes |
| − | | | + | |x8616=Yes |
| − | | | + | |x8632=Yes |
| − | | | + | |x8664=Yes |
| − | | | + | |nx=Yes |
| − | | | + | |mmx=Yes |
| − | | | + | |emmx=Yes |
| − | | | + | |sse=Yes |
| − | | | + | |sse2=Yes |
| − | | | + | |sse3=Yes |
| − | | | + | |ssse3=Yes |
| − | | | + | |sse41=Yes |
| − | | | + | |sse42=Yes |
| − | | | + | |sse4a=No |
| − | | | + | |avx=Yes |
| − | | | + | |avx2=Yes |
| − | | | + | |
| − | | | + | |abm=Yes |
| − | | | + | |tbm=No |
| − | | | + | |bmi1=Yes |
| − | | | + | |bmi2=Yes |
| − | | | + | |fma3=Yes |
| − | | | + | |fma4=No |
| − | | | + | |aes=Yes |
| − | | | + | |rdrand=Yes |
| − | | | + | |sha=No |
| − | | mpx | + | |xop=No |
| − | | sgx | + | |adx=Yes |
| − | | | + | |clmul=Yes |
| − | | | + | |f16c=Yes |
| − | | | + | |tbt1=No |
| + | |tbt2=Yes | ||
| + | |tbmt3=No | ||
| + | |bpt=No | ||
| + | |eist=Yes | ||
| + | |sst=No | ||
| + | |flex=No | ||
| + | |fastmem=No | ||
| + | |isrt=No | ||
| + | |sba=No | ||
| + | |mwt=No | ||
| + | |sipp=No | ||
| + | |att=No | ||
| + | |ipt=No | ||
| + | |tsx=Yes | ||
| + | |txt=Yes | ||
| + | |ht=No | ||
| + | |vpro=Yes | ||
| + | |vtx=Yes | ||
| + | |vtd=Yes | ||
| + | |ept=Yes | ||
| + | |mpx=Yes | ||
| + | |sgx=Yes | ||
| + | |securekey=Yes | ||
| + | |osguard=Yes | ||
| + | |3dnow=No | ||
| + | |e3dnow=No | ||
| + | |smartmp=No | ||
| + | |powernow=No | ||
| + | |amdvi=No | ||
| + | |amdv=No | ||
| + | |amdsme=No | ||
| + | |amdtsme=No | ||
| + | |amdsev=No | ||
| + | |rvi=No | ||
| + | |smt=No | ||
| + | |sensemi=No | ||
| + | |xfr=No | ||
}} | }} | ||
Latest revision as of 23:29, 6 April 2018
| Edit Values | ||||||||||||
| Xeon E3-1220 v5 | ||||||||||||
 | ||||||||||||
| General Info | ||||||||||||
| Designer | Intel | |||||||||||
| Manufacturer | Intel | |||||||||||
| Model Number | E3-1220 v5 | |||||||||||
| Part Number | CM8066201921804, BX80662E31220V5 | |||||||||||
| S-Spec | SR2CQ, SR2LG | |||||||||||
| Market | Server | |||||||||||
| Introduction | October 19, 2015 (announced) October 19, 2015 (launched) | |||||||||||
| End-of-life | October 26, 2018 (last order) April 12, 2019 (last shipment) | |||||||||||
| Release Price | $203.00 | |||||||||||
| Shop | Amazon | |||||||||||
| General Specs | ||||||||||||
| Family | Xeon E3 | |||||||||||
| Series | E3-1200 v5 | |||||||||||
| Locked | Yes | |||||||||||
| Frequency | 3,000 MHz | |||||||||||
| Turbo Frequency | Yes | |||||||||||
| Turbo Frequency | 3,500 MHz (1 core) | |||||||||||
| Bus type | DMI 3.0 | |||||||||||
| Bus rate | 4 × 8 GT/s | |||||||||||
| Clock multiplier | 30 | |||||||||||
| CPUID | 506E3 | |||||||||||
| Microarchitecture | ||||||||||||
| ISA | x86-64 (x86) | |||||||||||
| Microarchitecture | Skylake | |||||||||||
| Platform | Greenlow | |||||||||||
| Chipset | Sunrise Point | |||||||||||
| Core Name | Skylake DT | |||||||||||
| Core Family | 6 | |||||||||||
| Core Model | 94 | |||||||||||
| Core Stepping | R0 | |||||||||||
| Process | 14 nm | |||||||||||
| Technology | CMOS | |||||||||||
| Die | 122 mm² | |||||||||||
| Word Size | 64 bit | |||||||||||
| Cores | 4 | |||||||||||
| Threads | 4 | |||||||||||
| Max Memory | 64 GiB | |||||||||||
| Multiprocessing | ||||||||||||
| Max SMP | 1-Way (Uniprocessor) | |||||||||||
| Electrical | ||||||||||||
| Vcore | 0.55 V-1.52 V | |||||||||||
| TDP | 80 W | |||||||||||
| Tjunction | 0 °C – 100 °C | |||||||||||
| Tstorage | -25 °C – 125 °C | |||||||||||
| Packaging | ||||||||||||
| ||||||||||||
Xeon E3-1220 v5 is an entry-level server and workstation 64-bit quad-core x86 microprocessor introduced by Intel in October 2015. This Skylake-based chip operates at 3 GHz with turbo boost of 3.5 GHz. The E3-1220 v5 has a TDP of 80 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has no integrated graphics processor.
Cache[edit]
- Main article: Skylake § Cache
 |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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Graphics[edit]
This chip has no integrated graphics processing unit.
Features[edit]
[Edit/Modify Supported Features]
Facts about "Xeon E3-1220 v5 - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon E3-1220 v5 - Intel#io + |
| has ecc memory support | true + |
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
| max memory bandwidth | 35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) + |
| max memory channels | 2 + |
| max pcie lanes | 16 + |
| supported memory type | DDR3L-1600 + and DDR4-2133 + |