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Difference between revisions of "intel/xeon e3/e3-1268l v5"
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{{intel title|Xeon E3-1268L V5}}
+
{{intel title|Xeon E3-1268L v5}}
−
{{mpu
+
{{chip
−
| name               = Xeon E3-1268L V5
+
|name=Xeon E3-1268L v5
−
| no image           = Yes
+
|image=skylake dt (front).png
−
| image              =
+
|designer=Intel
−
| image size          =
+
|manufacturer=Intel
−
| caption            =  
+
|model number=E3-1268L v5
−
| designer           = Intel
+
|part number=CM8066201937901
−
| manufacturer       = Intel
+
|s-spec=SR2LQ
−
| model number       = E3-1268L V5
+
|market=Embedded
−
| part number         = CM8066201937901
+
|first announced=October 19, 2015
−
| part number 2      =  
+
|first launched=October 19, 2015
−
| market             = Embedded
+
|last order=October 26, 2018
−
| market 2            =
+
|last shipment=April 12, 2019
−
| first announced     = October 19, 2015
+
|release price=$377
−
| first launched     = October 19, 2015
+
|family=Xeon E3
−
| last order         =  
+
|series=E3-1200 v5
−
| last shipment       =  
+
|locked=Yes
−
| release price       = $377
+
|frequency=2,400 MHz
−
 
+
|turbo frequency1=3,400 MHz
−
| family             = Xeon E3
+
|turbo frequency2=3,300 MHz
−
| series             = E3-1200 V5
+
|turbo frequency3=3,200 MHz
−
| locked             = Yes
+
|turbo frequency4=3,100 MHz
−
| frequency           = 2400 MHz
+
|turbo frequency=Yes
−
| turbo frequency    = Yes
+
|bus type=DMI 3.0
−
| turbo frequency1    = 3400 MHz
+
|bus links=4
−
| turbo frequency2    =  
+
|bus rate=8 GT/s
−
| turbo frequency3    =  
+
|clock multiplier=24
−
| turbo frequency4    =  
+
|cpuid=506E3
−
| bus type           = DMI 3.0
+
|isa=x86-64
−
| bus speed          =  
+
|isa family=x86
−
| bus rate           = 8 GT/s
+
|microarch=Skylake
−
| clock multiplier   = 24
+
|platform=Greenlow
−
| s-spec              = SR2LQ
+
|chipset=Sunrise Point
−
| s-spec 2            =
+
|core name=Skylake DT
−
| s-spec es          =
+
|core family=6
−
| s-spec qs          =
+
|core model=94
−
| cpuid               = 506E3
+
|core stepping=R0
−
 
+
|process=14 nm
−
| isa family          = x86
+
|technology=CMOS
−
| isa                 = x86-64
+
|die area=122 mm²
−
| microarch           = Skylake
+
|word size=64 bit
−
| platform           = Greenlow
+
|core count=4
−
| chipset             = Silver Pass
+
|thread count=8
−
| core name           = Skylake DT
+
|max cpus=1
−
| core family         = 6
+
|max memory=64 GiB
−
| core model         = 14
+
|v core min=0.55 V
−
| core stepping       = R0
+
|v core max=1.52 V
−
| process             = 14 nm
+
|tdp=35 W
−
| transistors        =
+
|tjunc min=0 °C
−
| technology         = CMOS
+
|tjunc max=100 °C
−
| die area           = 122 mm²
+
|tstorage min=-25 °C
−
| word size           = 64 bit
+
|tstorage max=125 °C
−
| core count         = 4
+
|package module 1={{packages/intel/lga-1151}}
−
| thread count       = 8
 
−
| max cpus           = 1
 
−
| max memory         = 64 GiB
 
−
 
 
−
| electrical          = Yes
 
−
| v core             =  
 
−
| v core tolerance    =
 
−
| sdp                =  
 
−
| tdp                 = 35 W
 
−
| tjunc min           = 0 °C
 
−
| tjunc max           = 100 °C
 
−
| tcase min          =
 
−
| tcase max          =
 
−
| tstorage min       = -25 °C
 
−
| tstorage max       = 125 °C
 
−
| tambient min        =
 
−
| tambient max        =
 
−
 
 
−
| packaging          = Yes
 
−
| package             = FCLGA1151
 
−
| package type        = FCLGA
 
−
| package size        = 37.5mm x 37.5mm
 
−
| socket              = LGA1151
 
−
| socket type        = LGA
 
 
}}
 
}}
−
'''Xeon E3-1268L V5''' is an entry-level server and workstation {{arch|64}} [[quad-core]] [[x86]] microprocessor introduced by [[Intel]] in October 2015. This {{intel|Skylake}}-based chip operates at 2.4 GHz with turbo boost of 3.4 GHz. The E3-1268L V5 is an ultra low power chip with a TDP of 35 Watts and supports up to 64 GB of dual-channel DDR3/4. This MPU has the {{intel|HD Graphics P530}} [[integrated graphics processor|IGP]] underclocked to 350 MHz.
+
'''Xeon E3-1268L v5''' is an entry-level server and workstation {{arch|64}} [[quad-core]] [[x86]] microprocessor introduced by [[Intel]] in October 2015. This {{intel|Skylake}}-based chip operates at 2.4 GHz with turbo boost of 3.4 GHz. The E3-1268L v5 is an ultra low power chip with a TDP of 35 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has the {{intel|HD Graphics P530}} [[integrated graphics processor|IGP]] underclocked to 350 MHz.
  
 
== Cache ==
 
== Cache ==
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|l3 cache=8 MiB
 
|l3 cache=8 MiB
 
|l3 break=4x2 MiB
 
|l3 break=4x2 MiB
−
|l3 desc=16-way set associative
 
 
|l3 policy=write-back
 
|l3 policy=write-back
 
}}
 
}}
Line 103: Line 78:
 
== Memory controller ==
 
== Memory controller ==
 
{{memory controller
 
{{memory controller
−
|type=DDR3L-1600  
+
|type=DDR3L-1600
 
|type 2=DDR4-2133
 
|type 2=DDR4-2133
 
|ecc=Yes
 
|ecc=Yes
Line 109: Line 84:
 
|controllers=1
 
|controllers=1
 
|channels=2
 
|channels=2
−
|max bandwidth=35.76 GiB/s
+
|max bandwidth=31.79 GiB/s
−
|bandwidth schan=17.88 GiB/s
+
|bandwidth schan=15.89 GiB/s
−
|bandwidth dchan=35.76 GiB/s
+
|bandwidth dchan=31.79 GiB/s
 +
}}
 +
 
 +
== Expansions ==
 +
{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 16
 +
| pcie config        = 1x16
 +
| pcie config 2      = 2x8
 +
| pcie config 3      = 1x8+2x4
 
}}
 
}}
  
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| edp ver            = 1.3
 
| edp ver            = 1.3
 
| max res hdmi      = 4096x2304
 
| max res hdmi      = 4096x2304
−
| max res hdmi freq  = 30 Hz
+
| max res hdmi freq  = 24 Hz
 
| max res dp        = 4096x2304
 
| max res dp        = 4096x2304
 
| max res dp freq    = 60 Hz
 
| max res dp freq    = 60 Hz
Line 160: Line 144:
 
{{skylake hardware accelerated video table|col=1}}
 
{{skylake hardware accelerated video table|col=1}}
  
−
== Expansions ==
+
== Features ==
−
{{mpu expansions
+
{{x86 features
−
| pcie revision      = 3.0
+
|real=Yes
−
| pcie lanes        = 16
+
|protected=Yes
−
| pcie config        = 1x16
+
|smm=Yes
−
| pcie config 1      = 2x8
+
|fpu=Yes
−
| pcie config 2      = 1x8+2x4
+
|x8616=Yes
−
| usb revision      =  
+
|x8632=Yes
−
| usb revision 2    =  
+
|x8664=Yes
−
| usb revision N    =  
+
|nx=Yes
−
| usb ports          =  
+
|mmx=Yes
−
| sata ports        =  
+
|emmx=Yes
−
| integrated lan    =  
+
|sse=Yes
−
| uart              =  
+
|sse2=Yes
−
}}
+
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=Yes
 +
|avx2=Yes
  
−
== Features ==  
+
|abm=Yes
−
{{mpu features
+
|tbm=No
−
| em64t      = Yes
+
|bmi1=Yes
−
| nx          = Yes
+
|bmi2=Yes
−
| txt        = Yes
+
|fma3=Yes
−
| tsx        = Yes
+
|fma4=No
−
| vpro        = Yes
+
|aes=Yes
−
| ht          = Yes
+
|rdrand=Yes
−
| tbt1       =
+
|sha=No
−
| tbt2       = Yes
+
|xop=No
−
| bpt         =  
+
|adx=Yes
−
| vt-x        = Yes
+
|clmul=Yes
−
| vt-d        = Yes
+
|f16c=Yes
−
| ept        = Yes
+
|tbt1=No
−
| mmx        = Yes
+
|tbt2=Yes
−
| sse        = Yes
+
|tbmt3=No
−
| sse2        = Yes
+
|bpt=No
−
| sse3        = Yes
+
|eist=Yes
−
| ssse3      = Yes
+
|sst=No
−
| sse4        = Yes
+
|flex=No
−
| sse4.1      = Yes
+
|fastmem=No
−
| sse4.2      = Yes
+
|isrt=No
−
| aes        = Yes
+
|sba=No
−
| pclmul      = Yes
+
|mwt=No
−
| avx        = Yes
+
|sipp=No
−
| avx2        = Yes
+
|att=No
−
| bmi        = Yes
+
|ipt=No
−
| bmi1        = Yes
+
|tsx=Yes
−
| bmi2        = Yes
+
|txt=Yes
−
| f16c        = Yes
+
|ht=Yes
−
| fma3        = Yes
+
|vpro=Yes
−
| mpx        = Yes
+
|vtx=Yes
−
| sgx        = Yes
+
|vtd=Yes
−
| eist        = Yes
+
|ept=Yes
−
| secure key  = Yes
+
|mpx=Yes
−
| os guard    = Yes
+
|sgx=Yes
 +
|securekey=Yes
 +
|osguard=Yes
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 
}}
 
}}

Latest revision as of 23:27, 6 April 2018

Edit Values
Xeon E3-1268L v5
skylake dt (front).png
General Info
DesignerIntel
ManufacturerIntel
Model NumberE3-1268L v5
Part NumberCM8066201937901
S-SpecSR2LQ
MarketEmbedded
IntroductionOctober 19, 2015 (announced)
October 19, 2015 (launched)
End-of-lifeOctober 26, 2018 (last order)
April 12, 2019 (last shipment)
Release Price$377
ShopAmazon
General Specs
FamilyXeon E3
SeriesE3-1200 v5
LockedYes
Frequency2,400 MHz
Turbo FrequencyYes
Turbo Frequency3,400 MHz (1 core),
3,300 MHz (2 cores),
3,200 MHz (3 cores),
3,100 MHz (4 cores)
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier24
CPUID506E3
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureSkylake
PlatformGreenlow
ChipsetSunrise Point
Core NameSkylake DT
Core Family6
Core Model94
Core SteppingR0
Process14 nm
TechnologyCMOS
Die122 mm²
Word Size64 bit
Cores4
Threads8
Max Memory64 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore0.55 V-1.52 V
TDP35 W
Tjunction0 °C – 100 °C
Tstorage-25 °C – 125 °C
Packaging
PackageFCLGA-1151 (LGA)
FC-LGA14C		FCLGA-1151.svg
Dimension37.5 mm x 37.5 mm x 4.4 mm
Pitch0.914 mm
Contacts1151
SocketLGA-1151

Xeon E3-1268L v5 is an entry-level server and workstation 64-bit quad-core x86 microprocessor introduced by Intel in October 2015. This Skylake-based chip operates at 2.4 GHz with turbo boost of 3.4 GHz. The E3-1268L v5 is an ultra low power chip with a TDP of 35 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has the HD Graphics P530 IGP underclocked to 350 MHz.

Cache[edit]

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associativewrite-back
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  4x256 KiB4-way set associativewrite-back
L3$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  4x2 MiB write-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3L-1600, DDR4-2133
Supports ECCYes
Max Mem64 GiB
Controllers1
Channels2
Max Bandwidth31.79 GiB/s
32,552.96 MiB/s
34.134 GB/s
34,134.253 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes16
Configs1x16, 2x8, 1x8+2x4


Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUHD Graphics P530
DesignerIntelDevice ID0x191D
Execution Units24Max Displays3
Max Memory1.7 GiB
1,740.8 MiB
1,782,579.2 KiB
1,825,361,100.8 B
Frequency350 MHz
0.35 GHz
350,000 KHz
Burst Frequency1,000 MHz
1 GHz
1,000,000 KHz
OutputDP, eDP, HDMI, DVI
Max Resolution
HDMI4096x2304 @24 Hz
DP4096x2304 @60 Hz
eDP4096x2304 @60 Hz
Standards
DirectX12
OpenGL4.4
OpenCL2.0
DP1.2
eDP1.3
HDMI1.4a
Additional Features
Intel Quick Sync Video
Intel InTru 3D
Intel Clear Video
Intel Clear Video HD

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
MPXMemory Protection Extensions
SGXSoftware Guard Extensions
Secure KeySecure Key Technology
SMEPOS Guard Technology
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e3/e3-1268l_v5&oldid=76967"
Facts about "Xeon E3-1268L v5 - Intel"
RDF feed
device id0x191D +
has ecc memory supporttrue +
integrated gpuHD Graphics P530 +
integrated gpu base frequency350 MHz (0.35 GHz, 350,000 KHz) +
integrated gpu designerIntel +
integrated gpu execution units24 +
integrated gpu max frequency1,000 MHz (1 GHz, 1,000,000 KHz) +
integrated gpu max memory1,740.8 MiB (1,782,579.2 KiB, 1,825,361,100.8 B, 1.7 GiB) +
l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ description16-way set associative +
l3$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
max memory bandwidth35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) +
max memory channels2 +
supported memory typeDDR3L-1600 + and DDR4-2133 +