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Difference between revisions of "Template:verilog guide"
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* {{verilog|Simulator}} | * {{verilog|Simulator}} | ||
* {{verilog|Testbench}} | * {{verilog|Testbench}} | ||
− | <div class="header">Modules</div> | + | <div class="header">Modules<small style="float: right;">({{verilog|Modules|All}})</small></div> |
* {{verilog|ADC}} | * {{verilog|ADC}} | ||
* {{verilog|MUX}} | * {{verilog|MUX}} |
Revision as of 11:24, 27 March 2018
Basics
Language
Gate Level Modeling
Behavioral Modeling
- Always Block
- Procedural Assignments
- Continuous Assignments
- Conditional Statement
- Case Statement
- Looping Statements
- Looping Statements
Testing
Modules(All)
- v · d · e