Revision as of 16:22, 26 March 2018

Verilog is a hardware description and a verification language designed for describing, modeling and simulating digital circuits. It is used in early front-end IC design.

History

Verilog has a few iterations: Verilog 95, Verilog 2001, Verilog 2005 and SystemVerilog. All of the new revisions have added something new and useful. The latest update was a SystemVerilog(SV). It was declared that SV is a superset of Verilog, and it is backwards compatible with it. That means that all of Verilog code can be run in SystemVerilog simulators and design tools. Only thing that SV added is better Verification methodology like UVM and OVM style of testbenches.

Syntax

Verilog is a static, weakly typed style language similar to C in some aspects. It is case sensitive(meaning that there is difference between "a" and "A"), has preprocessor and has control flow keywords(allowing for if,else, for, while etc. statements to be implemented).

The basic look of every module is like the following:

module n //module name
  module n declaration //declaration of the ports
endmodule //ending

In Verilog, you use // to add commentary on the line you wish to high lite

Now we are going to make basic AND gate. First, we need to know how the AND gate looks, what it does and how it operates. When you need to know that about some other module, but you don't, easiest way around it is to google the module. But when you find code, don't copy it, but rather study it. Write down the characteristics of it and start building the module in your head.

AND gate takes A and B input and combines them into output Y, so based on that we do the following

module andgate (a, b, y)#(parameter WIDTH = 1)(; // module name with width measurement(ex. 16bit)
  input[WIDTH 1:0] a; //(a)input of the module
  input[WIDTH 1:0] b; //(b)input of the module
  output[WIDTH 1:0] y; //module output
  assign y = a & b; //assigned operation of the module 
endmodule

We can note a few thing from this example. First, at the end of each line, we use semicolon(;). And second, you may notice that there is assign operation which tells the module what to do. In this case, it told the module that y equaled the sum of a & b. Also a thing to note that when we need to add a width of a module(16, 32, 64, 128 bit...), we add it using #(parameter WIDTH = n)

When module is created, it needs to be verified. For the process of verification, we need to write a testbench.

There is an extension to the Verilog, its superset, SystemVerilog. Its primary usage is verification using different methods like UVM and OVM, but you can verify your design using this "regular" kind of verilog.

module andgate_tb // "_tb" suffix added to indicate the testbench
  reg[3:0] a, b; //reg is input of the module
  wire[3:0] y; //wire is the output of the module
  andgate(
  .a(a),
  .b(b),
  .y(y)
  );
 initial begin //starts the simulation od module
 //since the [3:0] is a 4 bit input, we use 4 and than "b" which indicates binary system
 //we have a binary system that follows different combinations after the "4'b"  
    a = 4'b0000; 
    b = 4'b0000; 
    #10
    a = 4'b1111;
    b = 4'b0101;
    #10
    a = 4'b1100;
    b = 4'b1111;
    #10
    a = 4'b1100;
    b = 4'b0011;
    #10
    a = 4'b1100;
    b = 4'b1010;
    #10
    $finish;
  end //ends the simulation of module

The #10 indicates the unit of time. It is a measurement which tells how much is the module going to be triggered. The $finish line indicates the finish of the simulation.

File type

Verilog is using .v file system or .sv if SystemVerilog is in question