From WikiChip
Difference between revisions of "intel/xeon d/d-2146nt"
< intel‎ | xeon d

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{{unknown features}}
 
{{unknown features}}
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== Cache ==
 
== Cache ==
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|l3 desc=11-way set associative
 
|l3 desc=11-way set associative
 
|l3 policy=write-back
 
|l3 policy=write-back
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}}
 
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== Memory controller ==
 
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{{memory controller
 
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|type=DDR4-2666
 
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|ecc=Yes
 
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|max mem=512 GiB
 
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|controllers=2
 
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|channels=4
 
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|max bandwidth=79.47 GiB/s
 
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|bandwidth schan=19.87 GiB/s
 
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|bandwidth dchan=39.74 GiB/s
 
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|bandwidth qchan=79.47 GiB/s
 
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}}
 
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== Expansions ==
 
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{{expansions main
 
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|
 
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{{expansions entry
 
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|type=PCIe
 
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|pcie revision=3.0
 
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|pcie lanes=48
 
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|pcie config=x16
 
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|pcie config 2=x8
 
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|pcie config 3=x4
 
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}}
 
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}}
 
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== Features ==
 
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{{x86 features
 
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|real=Yes
 
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|protected=Yes
 
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|smm=Yes
 
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|fpu=Yes
 
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|x8616=Yes
 
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|x8632=Yes
 
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|x8664=Yes
 
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|nx=Yes
 
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|mmx=Yes
 
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|emmx=Yes
 
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|sse=Yes
 
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|sse2=Yes
 
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|sse3=Yes
 
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|ssse3=Yes
 
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|sse41=Yes
 
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|sse42=Yes
 
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|sse4a=No
 
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|avx=Yes
 
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|avx2=Yes
 
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|avx512f=Yes
 
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|avx512cd=Yes
 
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|avx512er=No
 
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|avx512pf=No
 
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|avx512bw=Yes
 
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|avx512dq=Yes
 
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|avx512vl=Yes
 
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|avx512ifma=No
 
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|avx512vbmi=No
 
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|avx5124fmaps=No
 
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|avx5124vnniw=No
 
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|avx512vpopcntdq=No
 
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|avx512units=2
 
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|abm=Yes
 
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|tbm=No
 
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|bmi1=Yes
 
−
|bmi2=Yes
 
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|fma3=Yes
 
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|fma4=No
 
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|aes=Yes
 
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|rdrand=Yes
 
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|sha=No
 
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|xop=No
 
−
|adx=Yes
 
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|clmul=Yes
 
−
|f16c=Yes
 
−
|tbt1=No
 
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|tbt2=Yes
 
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|tbmt3=No
 
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|bpt=No
 
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|eist=Yes
 
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|sst=Yes
 
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|flex=No
 
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|fastmem=No
 
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|ivmd=Yes
 
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|intelnodecontroller=No
 
−
|intelnode=No
 
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|kpt=No
 
−
|ptt=No
 
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|intelrunsure=No
 
−
|mbe=No
 
−
|isrt=No
 
−
|sba=No
 
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|mwt=No
 
−
|sipp=No
 
−
|att=No
 
−
|ipt=Yes
 
−
|tsx=Yes
 
−
|txt=Yes
 
−
|ht=Yes
 
−
|vpro=Yes
 
−
|vtx=Yes
 
−
|vtd=Yes
 
−
|ept=Yes
 
−
|mpx=Yes
 
−
|sgx=No
 
−
|securekey=Yes
 
−
|osguard=Yes
 
−
|intqat=No
 
−
|3dnow=No
 
−
|e3dnow=No
 
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|smartmp=No
 
−
|powernow=No
 
−
|amdvi=No
 
−
|amdv=No
 
−
|amdsme=No
 
−
|amdtsme=No
 
−
|amdsev=No
 
−
|rvi=No
 
−
|smt=No
 
−
|sensemi=No
 
−
|xfr=No
 
 
}}
 
}}

Revision as of 15:00, 7 February 2018

Edit Values
Xeon D-2146NT
skylake-de (front).png
General Info
DesignerIntel
ManufacturerIntel
Model NumberD-2146NT
Part NumberFH8067303782601
S-SpecSR3ZR
MarketServer, Embedded
IntroductionFebruary 7, 2018 (announced)
February 7, 2018 (launched)
Release Price$641.00
ShopAmazon
General Specs
FamilyXeon D
SeriesD-2000
LockedYes
Frequency2,300 MHz
Turbo Frequency3,000 MHz (1 core)
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier23
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureSkylake (server)
Core NameSkylake-DE
Core SteppingM1
Process14 nm
TechnologyCMOS
MCPYes (2 dies)
Word Size64 bit
Cores8
Threads16
Max Memory512 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP80 W
Packaging
PackageFCBGA-2518 (BGA)
Dimension45 mm x 52.5 mm
Contacts2518

Xeon D-2146NT is a 64-bit 8-core high-performance x86 server microprocessor introduced by Intel in early 2018 for the dense server and edge computing market segment. Fabricated on Intel's 14 nm process based on the Skylake microarchitecture, this model operates at 2.3 GHz with a Turbo Boost of up to 3.0 GHz and a TDP of 80 W. The D-2146NT supports up to 512 GiB of quad-chanel DDR4-2133 ECC memory.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associativewrite-back
L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  8x1 MiB16-way set associativewrite-back
L3$11 MiB
11,264 KiB
11,534,336 B
0.0107 GiB
  8x1.375 MiB11-way set associativewrite-back
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Facts about "Xeon D-2146NT - Intel"
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Xeon D-2146NT - Intel#package +
base frequency2,300 MHz (2.3 GHz, 2,300,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
clock multiplier23 +
core count8 +
core nameSkylake-DE +
core steppingM1 +
designerIntel +
die count2 +
familyXeon D +
first announcedFebruary 7, 2018 +
first launchedFebruary 7, 2018 +
full page nameintel/xeon d/d-2146nt +
has locked clock multipliertrue +
instance ofmicroprocessor +
is multi-chip packagetrue +
isax86-64 +
isa familyx86 +
l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description16-way set associative +
l2$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description11-way set associative +
l3$ size11 MiB (11,264 KiB, 11,534,336 B, 0.0107 GiB) +
ldateFebruary 7, 2018 +
main imageFile:skylake-de (front).png +
manufacturerIntel +
market segmentServer + and Embedded +
max cpu count1 +
max memory524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) +
microarchitectureSkylake (server) +
model numberD-2146NT +
nameXeon D-2146NT +
packageFCBGA-2518 +
part numberFH8067303782601 +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 641.00 (€ 576.90, £ 519.21, ¥ 66,234.53) +
s-specSR3ZR +
seriesD-2000 +
smp max ways1 +
tdp80 W (80,000 mW, 0.107 hp, 0.08 kW) +
technologyCMOS +
thread count16 +
turbo frequency (1 core)3,000 MHz (3 GHz, 3,000,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +