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Difference between revisions of "samsung/microarchitectures/m3"
(→Key changes from {{\\|Mongoose 1}}/{{\\|Mongoose 2|M2}}) |
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*** 6-way decode (from 4) | *** 6-way decode (from 4) | ||
*** µOP fusion | *** µOP fusion | ||
− | **** | + | **** new fuse address generation and memory µOP support |
− | **** | + | **** new fuse literal generation µOP support |
** Back-end | ** Back-end | ||
*** Larger [[ReOrder buffer]] (228 entries, from 96 entries) | *** Larger [[ReOrder buffer]] (228 entries, from 96 entries) |
Revision as of 10:45, 5 February 2018
Edit Values | |
Mongoose 3 µarch | |
General Info | |
Arch Type | CPU |
Designer | Samsung |
Manufacturer | Samsung |
Introduction | 2018 |
Process | 10 nm |
Core Configs | 4 |
Pipeline | |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Decode | 6-way |
Instructions | |
ISA | ARMv8 |
Succession | |
Mongoose 3 (M3) is an ARM microarchitecture designed by Samsung for their consumer electronics serving as a successor to the Mongoose 2.
Contents
Process Technology
The M3 was fabricated on Samsung's second generation 10LPP (Low Power Plus) process.
Compiler support
Compiler | Arch-Specific | Arch-Favorable |
---|---|---|
GCC | -march=armv8-a+crypto |
-mtune=exynos-m3
|
Architecture
Key changes from Mongoose 1/M2
- 10nm 10LPP process (from 1st gen 10LPP)
- Core
- Front-end
- larger instruction queue (40 entries, up from 24)
- 6-way decode (from 4)
- µOP fusion
- new fuse address generation and memory µOP support
- new fuse literal generation µOP support
- Back-end
- Larger ReOrder buffer (228 entries, from 96 entries)
- New fastpath logical shift of up to 3 places
- Larger dispatch window (12 µOP/cycle, from 9)
- Larger Integer physical register file
- Larger FP physical register
- Integer cluster
- 9 pipes (from 7)
- New pipe for a second load unit added
- New pipe for a second ALU with 3-operand support and MUL/DIV
- 9 pipes (from 7)
- Floating Point cluster
- 3 pipes (From 3)
- Throughput of most FP operation have increased by 50%
- Additional EUs
- crypto EU, simple vector EU, vector shuffle/shift/mul, new FP store, new FP conversion
- 3 pipes (From 3)
- Memory subsystem
- 2x bandwidth (32B (2x16B)/cycle from 16B/cycle)
- fast paired 128-bit loads and stores
- 2x bandwidth (32B (2x16B)/cycle from 16B/cycle)
- Front-end
- branch misprediction penalty increased (16 cycles, from 14)
This list is incomplete; you can help by expanding it.
Memory Hierarchy
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This section is empty; you can help add the missing info by editing this page. |
Core
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This section is empty; you can help add the missing info by editing this page. |
All M3 Processors
List of M3-based Processors | ||||||||
---|---|---|---|---|---|---|---|---|
Main processor | Integrated Graphics | |||||||
Model | Family | Launched | Arch | Cores | Frequency | Turbo | GPU | Frequency |
Count: 0 |
References
- LLVM: lib/Target/AArch64/AArch64SchedExynosM3.td
Facts about "Exynos M3 - Microarchitectures - Samsung"
codename | Mongoose 3 + |
core count | 4 + |
designer | Samsung + |
first launched | 2018 + |
full page name | samsung/microarchitectures/m3 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8 + |
manufacturer | Samsung + |
microarchitecture type | CPU + |
name | Mongoose 3 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |