From WikiChip
Difference between revisions of "samsung/exynos/8890"
< samsung‎ | exynos

(+cache)
Line 29: Line 29:
 
}}
 
}}
 
'''Exynos 8 Octa (8890)''' is a {{arch|64}} [[octa-core]] high-performance mobile SoC designed by [[Samsung]] and introduced in early 2016 for their consumer electronics. Manufactured on a [[14 nm process]], the 8890 features [[eight cores]] consisting of a [[big core|big]] quad-core cluster operating at 2.3 GHz with a turbo of up to 2.6 GHz based on [[Samsung]]'s custom {{samsung|Mongoose 1|l=arch}} microarchitecture and another [[little core|little]] quad-core cluster operating at 1.6 GHz consisting of {{armh|Cortex-A53|l=arch}} cores. This chip supports up to 4 GiB of dual-channel 32-bit LPDDR4-3600 memory and incorporates a {{armh|Mali-T880}} MP12 GPU operating at 650 MHz. The 8890 incorporates an LTE modem supporting cat 12 download and cat 13 upload.
 
'''Exynos 8 Octa (8890)''' is a {{arch|64}} [[octa-core]] high-performance mobile SoC designed by [[Samsung]] and introduced in early 2016 for their consumer electronics. Manufactured on a [[14 nm process]], the 8890 features [[eight cores]] consisting of a [[big core|big]] quad-core cluster operating at 2.3 GHz with a turbo of up to 2.6 GHz based on [[Samsung]]'s custom {{samsung|Mongoose 1|l=arch}} microarchitecture and another [[little core|little]] quad-core cluster operating at 1.6 GHz consisting of {{armh|Cortex-A53|l=arch}} cores. This chip supports up to 4 GiB of dual-channel 32-bit LPDDR4-3600 memory and incorporates a {{armh|Mali-T880}} MP12 GPU operating at 650 MHz. The 8890 incorporates an LTE modem supporting cat 12 download and cat 13 upload.
 +
 +
== Cache ==
 +
{{main|samsung/microarchitectures/mongoose_1#Memory_Hierarchy|arm_holdings/microarchitectures/cortex-a53#Memory_Hierarchy|l1=Mongoose 1 § Cache||l2=Cortex-A53 § Cache}}
 +
For the {{samsung|Mongoose 1|l=arch}} core cluster:
 +
{{cache size
 +
|l1 cache=384 KiB
 +
|l1i cache=256 KiB
 +
|l1i break=6x64 KiB
 +
|l1i desc=4-way set associative
 +
|l1d cache=128 KiB
 +
|l1d break=4x32 KiB
 +
|l1d desc=8-way set associative
 +
|l2 cache=2 MiB
 +
|l2 break=1x2 MiB
 +
|l2 desc=16-way set associative
 +
}}
 +
 +
For the {{armh|Cortex-A53|l=arch}} cluster:
 +
 +
{{cache size
 +
|l1 cache=256 KiB
 +
|l1i cache=128 KiB
 +
|l1i break=4x32 KiB
 +
|l1i desc=2-way set associative
 +
|l1d cache=128 KiB
 +
|l1d break=4x32 KiB
 +
|l1d desc=4-way set associative
 +
|l2 cache=256 KiB
 +
|l2 break=1x256 KiB
 +
|l2 desc=16-way set associative
 +
}}

Revision as of 23:02, 4 February 2018

Edit Values
Exynos 8 Octa
exynos 8 octa.png
General Info
DesignerSamsung
ManufacturerSamsung
Model Number8890
MarketMobile
IntroductionNovember 12, 2015 (announced)
February 21, 2016 (launched)
General Specs
FamilyExynos
Series8
Frequency2,300 MHz
Turbo Frequency2,600 MHz (1 core),
2,600 MHz (2 cores),
2,300 MHz (3 cores),
2,300 MHz (4 cores)
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureMongoose 1, Cortex-A53
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores8
Threads8
Max Memory4 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)

Exynos 8 Octa (8890) is a 64-bit octa-core high-performance mobile SoC designed by Samsung and introduced in early 2016 for their consumer electronics. Manufactured on a 14 nm process, the 8890 features eight cores consisting of a big quad-core cluster operating at 2.3 GHz with a turbo of up to 2.6 GHz based on Samsung's custom Mongoose 1 microarchitecture and another little quad-core cluster operating at 1.6 GHz consisting of Cortex-A53 cores. This chip supports up to 4 GiB of dual-channel 32-bit LPDDR4-3600 memory and incorporates a Mali-T880 MP12 GPU operating at 650 MHz. The 8890 incorporates an LTE modem supporting cat 12 download and cat 13 upload.

Cache

Main articles: Mongoose 1 § Cache and Cortex-A53 § Cache

For the Mongoose 1 core cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$384 KiB
393,216 B
0.375 MiB
L1I$256 KiB
262,144 B
0.25 MiB
6x64 KiB4-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associative 
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  1x2 MiB16-way set associative 

For the Cortex-A53 cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB2-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB4-way set associative 
L2$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
  1x256 KiB16-way set associative 
Retrieved from "https://en.wikichip.org/w/index.php?title=samsung/exynos/8890&oldid=73648"
Facts about "Exynos 8 Octa (8890) - Samsung"
RDF feed
base frequency2,300 MHz (2.3 GHz, 2,300,000 kHz) +
core count8 +
designerSamsung +
familyExynos +
first announcedNovember 12, 2015 +
first launchedFebruary 21, 2016 +
full page namesamsung/exynos/8890 +
instance ofmicroprocessor +
isaARMv8 +
isa familyARM +
l1$ size384 KiB (393,216 B, 0.375 MiB) + and 256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative + and 4-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description4-way set associative + and 2-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) + and 128 KiB (131,072 B, 0.125 MiB) +
l2$ description16-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + and 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
ldateFebruary 21, 2016 +
main imageFile:exynos 8 octa.png +
manufacturerSamsung +
market segmentMobile +
max cpu count1 +
max memory4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
microarchitectureMongoose 1 + and Cortex-A53 +
model number8890 +
nameExynos 8 Octa +
process14 nm (0.014 μm, 1.4e-5 mm) +
series8 +
smp max ways1 +
technologyCMOS +
thread count8 +
turbo frequency (1 core)2,600 MHz (2.6 GHz, 2,600,000 kHz) +
turbo frequency (2 cores)2,600 MHz (2.6 GHz, 2,600,000 kHz) +
turbo frequency (3 cores)2,300 MHz (2.3 GHz, 2,300,000 kHz) +
turbo frequency (4 cores)2,300 MHz (2.3 GHz, 2,300,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +