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Difference between revisions of "intel/xeon d/d-2141i"
< intel‎ | xeon d

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== Cache ==
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{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
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{{cache size
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|l1 cache=512 KiB
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|l1i cache=256 KiB
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|l1i break=8x32 KiB
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|l1i desc=8-way set associative
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|l1d cache=256 KiB
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|l1d break=8x32 KiB
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|l1d desc=8-way set associative
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|l1d policy=write-back
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|l2 cache=8 MiB
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|l2 break=8x1 MiB
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|l2 desc=16-way set associative
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|l2 policy=write-back
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|l3 cache=11 MiB
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|l3 break=8x1.375 MiB
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|l3 desc=11-way set associative
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|l3 policy=write-back
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}}

Revision as of 21:15, 1 February 2018

Edit Values
Xeon D-2141I
General Info
DesignerIntel
ManufacturerIntel
Model NumberD-2141I
MarketServer, Embedded
Release Price$555
ShopAmazon
General Specs
FamilyXeon D
SeriesD-2000
LockedYes
Frequency2,200 MHz
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureSkylake (server)
Core NameSkylake-D
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores8
Threads16
Max Memory512 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP65 W

Xeon D-2141I is a 64-bit octa-core high-performance x86 microserver processor set to be introduced by Intel in early 2018. Fabricated on Intel's 14nm+ process based on the Skylake microarchitecture, this chip operates at 2.2 GHz with a TDP of 65 W.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associativewrite-back
L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  8x1 MiB16-way set associativewrite-back
L3$11 MiB
11,264 KiB
11,534,336 B
0.0107 GiB
  8x1.375 MiB11-way set associativewrite-back
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_d/d-2141i&oldid=73517"
Facts about "Xeon D-2141I - Intel"
RDF feed
base frequency2,200 MHz (2.2 GHz, 2,200,000 kHz) +
core count8 +
core nameSkylake-D +
designerIntel +
familyXeon D +
full page nameintel/xeon d/d-2141i +
has locked clock multipliertrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description16-way set associative +
l2$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description11-way set associative +
l3$ size11 MiB (11,264 KiB, 11,534,336 B, 0.0107 GiB) +
ldate3000 +
manufacturerIntel +
market segmentServer + and Embedded +
max cpu count1 +
max memory524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) +
microarchitectureSkylake (server) +
model numberD-2141I +
nameXeon D-2141I +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 555.00 (€ 499.50, £ 449.55, ¥ 57,348.15) +
seriesD-2000 +
smp max ways1 +
tdp65 W (65,000 mW, 0.0872 hp, 0.065 kW) +
technologyCMOS +
thread count16 +
word size64 bit (8 octets, 16 nibbles) +