From WikiChip
Difference between revisions of "intel/xeon d/d-2146nt"
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+ | == Cache == | ||
+ | {{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=512 KiB | ||
+ | |l1i cache=256 KiB | ||
+ | |l1i break=8x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=256 KiB | ||
+ | |l1d break=8x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=8 MiB | ||
+ | |l2 break=8x1 MiB | ||
+ | |l2 desc=16-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=11 MiB | ||
+ | |l3 break=8x1.375 MiB | ||
+ | |l3 desc=11-way set associative | ||
+ | |l3 policy=write-back | ||
+ | }} |
Revision as of 22:15, 1 February 2018
Edit Values | |
Xeon D-2146NT | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | D-2146NT |
Market | Server, Embedded |
Shop | Amazon |
General Specs | |
Family | Xeon D |
Series | D-2000 |
Locked | Yes |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Skylake (server) |
Core Name | Skylake-D |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 8 |
Threads | 16 |
Max Memory | 512 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Xeon D-2146NT is a 64-bit octa-core high-performance x86 microserver processor set to be introduced by Intel in early 2018. Fabricated on Intel's 14nm+ process based on the Skylake microarchitecture, this chip operates at ? GHz with a TDP of ? W.
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Xeon D-2146NT - Intel"
core count | 8 + |
core name | Skylake-D + |
designer | Intel + |
family | Xeon D + |
full page name | intel/xeon d/d-2146nt + |
has locked clock multiplier | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 11 MiB (11,264 KiB, 11,534,336 B, 0.0107 GiB) + |
ldate | 3000 + |
manufacturer | Intel + |
market segment | Server + and Embedded + |
max cpu count | 1 + |
max memory | 524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) + |
microarchitecture | Skylake (server) + |
model number | D-2146NT + |
name | Xeon D-2146NT + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
series | D-2000 + |
smp max ways | 1 + |
technology | CMOS + |
thread count | 16 + |
word size | 64 bit (8 octets, 16 nibbles) + |