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Difference between revisions of "via technologies/microarchitectures/isaiah ii"
| Line 8: | Line 8: | ||
|cores=2 | |cores=2 | ||
|cores 2=4 | |cores 2=4 | ||
| − | |isa=x86- | + | |isa=x86-64 |
|predecessor=Isaiah | |predecessor=Isaiah | ||
|predecessor link=via technologies/microarchitectures/isaiah | |predecessor link=via technologies/microarchitectures/isaiah | ||
Revision as of 21:49, 14 January 2018
| Edit Values | |
| Isaiah II µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | VIA Technologies |
| Manufacturer | TSMC |
| Process | 28 nm |
| Core Configs | 2, 4 |
| Instructions | |
| ISA | x86-64 |
| Succession | |
Isaiah II is the successor to Isaiah, an x86 microarchitecture designed by VIA Technologies for low power devices.
Retrieved from "https://en.wikichip.org/w/index.php?title=via_technologies/microarchitectures/isaiah_ii&oldid=72541"
Facts about "Isaiah II - Microarchitectures - VIA Technologies"
| codename | Isaiah II + |
| core count | 2 + and 4 + |
| designer | VIA Technologies + |
| full page name | via technologies/microarchitectures/isaiah ii + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Isaiah II + |
| process | 28 nm (0.028 μm, 2.8e-5 mm) + |