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Difference between revisions of "esperanto/microarchitectures/et-minion"
| Line 20: | Line 20: | ||
|predecessor=BOOM v2 | |predecessor=BOOM v2 | ||
|predecessor link=uc berkeley/microarchitectures/boom v2 | |predecessor link=uc berkeley/microarchitectures/boom v2 | ||
| + | |contemporary=ET-Maxion | ||
| + | |contemporary link=esperanto/microarchitectures/et-maxion | ||
}} | }} | ||
Revision as of 20:09, 25 December 2017
| Edit Values | |
| ET-Minion µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Esperanto |
| Manufacturer | TSMC |
| Introduction | 2018 |
| Process | 7 nm |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Instructions | |
| ISA | RV64 |
| Extensions | I, M, A, F, D, C |
| Succession | |
| Contemporary | |
| ET-Maxion | |
Retrieved from "https://en.wikichip.org/w/index.php?title=esperanto/microarchitectures/et-minion&oldid=71572"
Facts about "ET-Minion - Microarchitectures - Esperanto"
| codename | ET-Minion + |
| designer | Esperanto + |
| first launched | 2018 + |
| full page name | esperanto/microarchitectures/et-minion + |
| instance of | microarchitecture + |
| instruction set architecture | RV64 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | ET-Minion + |
| process | 7 nm (0.007 μm, 7.0e-6 mm) + |