From WikiChip
Difference between revisions of "renesas/r-car/l1"
< renesas‎ | r-car

m (Bot: moving all {{mpu}} to {{chip}})
 
(2 intermediate revisions by one other user not shown)
Line 1: Line 1:
 
{{renesas title|R-Car L1}}
 
{{renesas title|R-Car L1}}
−
{{mpu
+
{{chip
 
|name=R-Car L1
 
|name=R-Car L1
 
|no image=Yes
 
|no image=Yes
Line 27: Line 27:
 
}}
 
}}
 
'''R-Car L1''' is a performance embedded SoC for the automotive industry designed by [[Renesas]]. The L1 features a single {{armh|Cortex-A9|l=arch}} core operating at 400 MHz. This chip incorporates [[Imagination]]'s {{imgtec|PowerVR SGX531}} [[GPU]]. This SoC supports up to 1 GiB of DDR3-1066 memory.
 
'''R-Car L1''' is a performance embedded SoC for the automotive industry designed by [[Renesas]]. The L1 features a single {{armh|Cortex-A9|l=arch}} core operating at 400 MHz. This chip incorporates [[Imagination]]'s {{imgtec|PowerVR SGX531}} [[GPU]]. This SoC supports up to 1 GiB of DDR3-1066 memory.
 +
 +
* '''Note:''' It's unknown if this model was ever actually released.
 +
 +
 +
== Cache ==
 +
{{main|arm holdings/microarchitectures/cortex-a9#Memory_Hierarchy|l1=Cortex-A9 § Cache}}
 +
{{cache size
 +
|l1 cache=64 KiB
 +
|l1i cache=32 KiB
 +
|l1i break=1x32 KiB
 +
|l1i desc=4-way set associative
 +
|l1d cache=32 KiB
 +
|l1d break=1x32 KiB
 +
|l1d desc=4-way set associative
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR3-1066
 +
|type 2=DDR2-533
 +
|ecc=No
 +
|max mem=1 GiB
 +
|controllers=1
 +
|channels=1
 +
|width=32 bit
 +
|max bandwidth=1.99 GiB/s
 +
|bandwidth schan=1.99 GiB/s
 +
}}
 +
 +
== Graphics ==
 +
{{integrated graphics
 +
| gpu                = PowerVR SGX531
 +
| designer            = Imagination Technologies
 +
| execution units    = 1
 +
 +
| opengl es ver      = 2.0
 +
}}
 +
 +
== Features ==
 +
{{arm features
 +
|thumb=No
 +
|thumb2=Yes
 +
|thumbee=Yes
 +
|vfpv1=No
 +
|vfpv2=No
 +
|vfpv3=Yes
 +
|vfpv3-d16=No
 +
|vfpv3-f16=No
 +
|vfpv4=No
 +
|vfpv4-d16=No
 +
|vfpv5=No
 +
|neon=Yes
 +
|jazelle=Yes
 +
|wmmx=No
 +
|wmmx2=No
 +
}}

Latest revision as of 15:32, 13 December 2017

Edit Values
R-Car L1
General Info
DesignerRenesas,
ARM Holdings
ManufacturerTSMC
Model NumberL1
MarketEmbedded
General Specs
FamilyR-Car
Series1st Gen
Frequency400 MHz
Microarchitecture
ISAARMv7 (ARM)
MicroarchitectureCortex-A9
Core NameCortex-A9
Process40 nm
TechnologyCMOS
Word Size32 bit
Cores1
Threads1
Max Memory1 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore1.2 V
VI/O3.3 V
Packaging
PackageFCBGA-429 (BGA)
Dimension18 mm x 18 mm
Pitch0.80 mm
Ball Count429
InterconnectBGA-429

R-Car L1 is a performance embedded SoC for the automotive industry designed by Renesas. The L1 features a single Cortex-A9 core operating at 400 MHz. This chip incorporates Imagination's PowerVR SGX531 GPU. This SoC supports up to 1 GiB of DDR3-1066 memory.

  • Note: It's unknown if this model was ever actually released.


Cache[edit]

Main article: Cortex-A9 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$64 KiB
65,536 B
0.0625 MiB
L1I$32 KiB
32,768 B
0.0313 MiB
1x32 KiB4-way set associative 
L1D$32 KiB
32,768 B
0.0313 MiB
1x32 KiB4-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1066, DDR2-533
Supports ECCNo
Max Mem1 GiB
Controllers1
Channels1
Width32 bit
Max Bandwidth1.99 GiB/s
2,037.76 MiB/s
2.137 GB/s
2,136.746 MB/s
0.00194 TiB/s
0.00214 TB/s
Bandwidth
Single 1.99 GiB/s

Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR SGX531
DesignerImagination Technologies
Execution Units1
Standards
OpenGL ES2.0

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
Thumb-2Thumb-2 Extension
ThumbEEThumb Execution Environment Extension
VFPv3Vector Floating Point (VFP) v3 Extension
NEONAdvanced SIMD extension
JazelleDirect Bytecode eXecution
Retrieved from "https://en.wikichip.org/w/index.php?title=renesas/r-car/l1&oldid=71195"
Facts about "R-Car L1 - Renesas"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
R-Car L1 - Renesas#package +
base frequency400 MHz (0.4 GHz, 400,000 kHz) +
core count1 +
core nameCortex-A9 +
core voltage1.2 V (12 dV, 120 cV, 1,200 mV) +
designerRenesas + and ARM Holdings +
familyR-Car +
full page namerenesas/r-car/l1 +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuPowerVR SGX531 +
integrated gpu designerImagination Technologies +
integrated gpu execution units1 +
io voltage3.3 V (33 dV, 330 cV, 3,300 mV) +
isaARMv7 +
isa familyARM +
l1$ size64 KiB (65,536 B, 0.0625 MiB) +
l1d$ description4-way set associative +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) +
l1i$ description4-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
ldate1900 +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory1,024 MiB (1,048,576 KiB, 1,073,741,824 B, 1 GiB, 9.765625e-4 TiB) +
max memory bandwidth1.99 GiB/s (2,037.76 MiB/s, 2.137 GB/s, 2,136.746 MB/s, 0.00194 TiB/s, 0.00214 TB/s) +
max memory channels1 +
microarchitectureCortex-A9 +
model numberL1 +
nameR-Car L1 +
packageFCBGA-429 +
process40 nm (0.04 μm, 4.0e-5 mm) +
series1st Gen +
smp max ways1 +
supported memory typeDDR3-1066 + and DDR2-533 +
technologyCMOS +
thread count1 +
word size32 bit (4 octets, 8 nibbles) +