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Difference between revisions of "intrinsity/fastmath/fastmath-lp"
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{{intrinsity title|FastMATH-LP}}
 
{{intrinsity title|FastMATH-LP}}
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{{mpu
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{{chip
 
| name                = FastMATH-LP
 
| name                = FastMATH-LP
 
| no image            =  
 
| no image            =  
−
| image              =  
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| image              = fastmath-lp chip.gif
 
| image size          =  
 
| image size          =  
 
| caption            =  
 
| caption            =  
 
| designer            = Intrinsity
 
| designer            = Intrinsity
 
| manufacturer        = TSMC
 
| manufacturer        = TSMC
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| model number        =  
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| model number        = FastMATH-LP
 
| part number        =  
 
| part number        =  
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| part number 1       =  
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| part number 2       =  
 
| market              = Embedded
 
| market              = Embedded
 
| first announced    = 2002
 
| first announced    = 2002
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| thread count        = 1
 
| thread count        = 1
 
| max cpus            =  
 
| max cpus            =  
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| max memory          =  
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| max memory          = 1 GiB
 
| max memory addr    =  
 
| max memory addr    =  
  
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| electrical          = Yes
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| power              = 6 W
 
| power              = 6 W
 
| v core              = 0.85 V
 
| v core              = 0.85 V
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}}
 
}}
 
The '''FastMATH-LP''' was a microprocessor developed by [[Intrinsity]] operating at 1 GHz. The processor incorporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit. This mode was a low-power (LP) version of the normal FastMATH processor, operating at half the speed.
 
The '''FastMATH-LP''' was a microprocessor developed by [[Intrinsity]] operating at 1 GHz. The processor incorporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit. This mode was a low-power (LP) version of the normal FastMATH processor, operating at half the speed.
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== Cache ==
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{{main|intrinsity/microarchitectures/fastmath#Memory_Hierarchy|l1=FastMATH § Cache}}
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{{cache info
 +
|l1i cache=16 KiB
 +
|l1i break=1x16 KiB
 +
|l1i desc=256 blocks × 16 words/block
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|l1d cache=16 KiB
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|l1d break=1x16 KiB
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|l1d desc=256 blocks × 16 words/block
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|l1d extra=write-through or write-back mode
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|l2 cache=1 MiB
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|l2 break=1x1 MiB
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|l2 desc=4-way set associative
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|l2 extra=(configurable as SRAM in 256 KiB increments)
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}}
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== Graphics ==
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This SoC has no integrated graphics processing unit.
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== Memory controller ==
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{{integrated memory controller
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| type              = DDR-400
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| controllers        = 1
 +
| channels          = 2
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| ecc support        =
 +
| max bandwidth      =
 +
| bandwidth schan    =
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| bandwidth dchan    =
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| max memory        = 1 GB
 +
}}
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== Matrix and Vector Unit ==
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* SIMD architecture
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* Operates on 4x4 array of {{arch|32}} elements
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* Fixed-point matrix, vector, and scalar data types
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 +
== Features ==
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* [[has feature::JTAG]] interface
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* 8-bit or 32-bit wide bus operates up to 66 MHz
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== Documents ==
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=== Manuals ===
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* [[:File:FastMATH Product Brief.pdf|FastMATH Product Brief]]
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 +
{{DEFAULTSORT:FastMATH, LP}}

Latest revision as of 16:31, 13 December 2017

Edit Values
FastMATH-LP
fastmath-lp chip.gif
General Info
DesignerIntrinsity
ManufacturerTSMC
Model NumberFastMATH-LP
MarketEmbedded
Introduction2002 (announced)
2003 (launched)
General Specs
FamilyFastMATH
Frequency1,000 MHz
Bus typeRapidIO
Bus speed500 MHz
Bus rate4 GT/s
Microarchitecture
MicroarchitectureFashMATH
Process130 nm
TechnologyDynamic CMOS
Word Size32 bit
Cores1
Threads1
Max Memory1 GiB
Electrical
Power dissipation6 W
Vcore0.85 V

The FastMATH-LP was a microprocessor developed by Intrinsity operating at 1 GHz. The processor incorporates a high-performance MIPS CPU along with a powerful matrix and vector math unit. This mode was a low-power (LP) version of the normal FastMATH processor, operating at half the speed.

Cache[edit]

Main article: FastMATH § Cache
Cache Info [Edit Values]
L1I$ 16 KiB
16,384 B
0.0156 MiB
1x16 KiB 256 blocks × 16 words/block
L1D$ 16 KiB
16,384 B
0.0156 MiB
1x16 KiB 256 blocks × 16 words/block write-through or write-back mode
L2$ 1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
1x1 MiB 4-way set associative (configurable as SRAM in 256 KiB increments)

Graphics[edit]

This SoC has no integrated graphics processing unit.

Memory controller[edit]

Integrated Memory Controller
Type DDR-400
Controllers 1
Channels 2
Max memory 1 GB

Matrix and Vector Unit[edit]

  • SIMD architecture
  • Operates on 4x4 array of 32-bit elements
  • Fixed-point matrix, vector, and scalar data types

Features[edit]

  • JTAG interface
  • 8-bit or 32-bit wide bus operates up to 66 MHz

Documents[edit]

Manuals[edit]


Retrieved from "https://en.wikichip.org/w/index.php?title=intrinsity/fastmath/fastmath-lp&oldid=71121"
Facts about "FastMATH-LP - Intrinsity"
RDF feed
base frequency1,000 MHz (1 GHz, 1,000,000 kHz) +
bus rate4,000 MT/s (4 GT/s, 4,000,000 kT/s) +
bus speed500 MHz (0.5 GHz, 500,000 kHz) +
bus typeRapidIO +
core count1 +
core voltage0.85 V (8.5 dV, 85 cV, 850 mV) +
designerIntrinsity +
familyFastMATH +
first announced2002 +
first launched2003 +
full page nameintrinsity/fastmath/fastmath-lp +
has featureJTAG +
instance ofmicroprocessor +
l1d$ description256 blocks × 16 words/block +
l1d$ size16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description256 blocks × 16 words/block +
l1i$ size16 KiB (16,384 B, 0.0156 MiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldate2003 +
main imageFile:fastmath-lp chip.gif +
manufacturerTSMC +
market segmentEmbedded +
max memory1,024 MiB (1,048,576 KiB, 1,073,741,824 B, 1 GiB, 9.765625e-4 TiB) +
microarchitectureFashMATH +
model numberFastMATH-LP +
nameFastMATH-LP +
power dissipation6 W (6,000 mW, 0.00805 hp, 0.006 kW) +
process130 nm (0.13 μm, 1.3e-4 mm) +
technologyDynamic CMOS +
thread count1 +
word size32 bit (4 octets, 8 nibbles) +