From WikiChip
Difference between revisions of "intrinsity/fastmath/fastmath-1.5"
< intrinsity‎ | fastmath

(Created page with "{{intrinsity title|FastMATH 1.5 GHz}} The '''FastMATH 1.5 GHz''' was a microprocessor developed by Intrinsity operating at 1.5 GHz. The processor incorporates a high-perfo...")
 
m (Bot: moving all {{mpu}} to {{chip}})
 
(11 intermediate revisions by 3 users not shown)
Line 1: Line 1:
 
{{intrinsity title|FastMATH 1.5 GHz}}
 
{{intrinsity title|FastMATH 1.5 GHz}}
 +
{{chip
 +
| name                = FastMATH 1.5 GHz
 +
| no image            = Yes
 +
| image              =
 +
| image size          =
 +
| caption            =
 +
| designer            = Intrinsity
 +
| manufacturer        = TSMC
 +
| model number        = FastMATH-1.5
 +
| part number        =
 +
| part number 2      =
 +
| market              = Embedded
 +
| first announced    = 2001
 +
| first launched      = 2002
 +
| last order          =
 +
| last shipment      =
 +
 +
| family              = FastMATH
 +
| series              =
 +
| locked              =
 +
| frequency          = 1,500 MHz
 +
| bus type            = RapidIO
 +
| bus speed          = 500 MHz
 +
| bus rate            = 4 GT/s
 +
| clock multiplier    =
 +
 +
| microarch          = FashMATH
 +
| platform            =
 +
| chipset            =
 +
| core name          =
 +
| core family        =
 +
| core model          =
 +
| core stepping      =
 +
| process            = 130 nm
 +
| transistors        =
 +
| technology          = Dynamic CMOS
 +
| die size            =
 +
| word size          = 32 bit
 +
| core count          = 1
 +
| thread count        = 1
 +
| max cpus            =
 +
| max memory          = 1 GiB
 +
| max memory addr    =
 +
 +
 +
| power              = 13.5 W
 +
| v core              = 1 V
 +
| v core tolerance    =
 +
| sdp                =
 +
| tdp                =
 +
| ctdp down          =
 +
| ctdp down frequency =
 +
| ctdp up            =
 +
| ctdp up frequency  =
 +
| temp min            =
 +
| temp max            =
 +
| tjunc min          =
 +
| tjunc max          =
 +
| tcase min          =
 +
| tcase max          =
 +
| tstorage min        =
 +
| tstorage max        =
 +
 +
| packaging          = Yes
 +
| package 0          = CBGA-670
 +
| package 0 type      = CBGA
 +
| package 0 pins      = 670
 +
| package 0 pitch    =
 +
| package 0 width    =
 +
| package 0 length    =
 +
| package 0 height    =
 +
| socket 0            =
 +
| socket 0 type      =
 +
}}
 
The '''FastMATH 1.5 GHz''' was a microprocessor developed by [[Intrinsity]] operating at 1.5 GHz. The processor incorporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit.
 
The '''FastMATH 1.5 GHz''' was a microprocessor developed by [[Intrinsity]] operating at 1.5 GHz. The processor incorporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit.
 +
 +
== Cache ==
 +
{{main|intrinsity/microarchitectures/fastmath#Memory_Hierarchy|l1=FastMATH § Cache}}
 +
{{cache info
 +
|l1i cache=16 KiB
 +
|l1i break=1x16 KiB
 +
|l1i desc=256 blocks × 16 words/block
 +
|l1d cache=16 KiB
 +
|l1d break=1x16 KiB
 +
|l1d desc=256 blocks × 16 words/block
 +
|l1d extra=write-through or write-back mode
 +
|l2 cache=1 MiB
 +
|l2 break=1x1 MiB
 +
|l2 desc=4-way set associative
 +
|l2 extra=(configurable as SRAM in 256 KiB increments)
 +
}}
 +
 +
== Graphics ==
 +
This SoC has no integrated graphics processing unit.
 +
 +
== Memory controller ==
 +
{{integrated memory controller
 +
| type              = DDR-400
 +
| controllers        = 1
 +
| channels          = 2
 +
| ecc support        =
 +
| max bandwidth      =
 +
| bandwidth schan    =
 +
| bandwidth dchan    =
 +
| max memory        = 1 GB
 +
}}
 +
 +
== Matrix and Vector Unit ==
 +
* SIMD architecture
 +
* Operates on 4x4 array of {{arch|32}} elements
 +
* Fixed-point matrix, vector, and scalar data types
 +
 +
== Features ==
 +
* [[has feature::JTAG]] interface
 +
* 8-bit or 32-bit wide bus operates up to 66 MHz
 +
 +
== Documents ==
 +
=== Manuals ===
 +
* [[:File:FastMATH Product Brief.pdf|FastMATH Product Brief]]
 +
 +
{{DEFAULTSORT:FastMATH, 1.5}}

Latest revision as of 15:30, 13 December 2017

Edit Values
FastMATH 1.5 GHz
General Info
DesignerIntrinsity
ManufacturerTSMC
Model NumberFastMATH-1.5
MarketEmbedded
Introduction2001 (announced)
2002 (launched)
General Specs
FamilyFastMATH
Frequency1,500 MHz
Bus typeRapidIO
Bus speed500 MHz
Bus rate4 GT/s
Microarchitecture
MicroarchitectureFashMATH
Process130 nm
TechnologyDynamic CMOS
Word Size32 bit
Cores1
Threads1
Max Memory1 GiB
Electrical
Power dissipation13.5 W
Vcore1 V

The FastMATH 1.5 GHz was a microprocessor developed by Intrinsity operating at 1.5 GHz. The processor incorporates a high-performance MIPS CPU along with a powerful matrix and vector math unit.

Cache[edit]

Main article: FastMATH § Cache
Cache Info [Edit Values]
L1I$ 16 KiB
16,384 B
0.0156 MiB
1x16 KiB 256 blocks × 16 words/block
L1D$ 16 KiB
16,384 B
0.0156 MiB
1x16 KiB 256 blocks × 16 words/block write-through or write-back mode
L2$ 1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
1x1 MiB 4-way set associative (configurable as SRAM in 256 KiB increments)

Graphics[edit]

This SoC has no integrated graphics processing unit.

Memory controller[edit]

Integrated Memory Controller
Type DDR-400
Controllers 1
Channels 2
Max memory 1 GB

Matrix and Vector Unit[edit]

  • SIMD architecture
  • Operates on 4x4 array of 32-bit elements
  • Fixed-point matrix, vector, and scalar data types

Features[edit]

  • JTAG interface
  • 8-bit or 32-bit wide bus operates up to 66 MHz

Documents[edit]

Manuals[edit]


Retrieved from "https://en.wikichip.org/w/index.php?title=intrinsity/fastmath/fastmath-1.5&oldid=71118"
Facts about "FastMATH 1.5 GHz - Intrinsity"
RDF feed
base frequency1,500 MHz (1.5 GHz, 1,500,000 kHz) +
bus rate4,000 MT/s (4 GT/s, 4,000,000 kT/s) +
bus speed500 MHz (0.5 GHz, 500,000 kHz) +
bus typeRapidIO +
core count1 +
core voltage1 V (10 dV, 100 cV, 1,000 mV) +
designerIntrinsity +
familyFastMATH +
first announced2001 +
first launched2002 +
full page nameintrinsity/fastmath/fastmath-1.5 +
has featureJTAG +
instance ofmicroprocessor +
l1d$ description256 blocks × 16 words/block +
l1d$ size16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description256 blocks × 16 words/block +
l1i$ size16 KiB (16,384 B, 0.0156 MiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldate2002 +
manufacturerTSMC +
market segmentEmbedded +
max memory1,024 MiB (1,048,576 KiB, 1,073,741,824 B, 1 GiB, 9.765625e-4 TiB) +
microarchitectureFashMATH +
model numberFastMATH-1.5 +
nameFastMATH 1.5 GHz +
power dissipation13.5 W (13,500 mW, 0.0181 hp, 0.0135 kW) +
process130 nm (0.13 μm, 1.3e-4 mm) +
technologyDynamic CMOS +
thread count1 +
word size32 bit (4 octets, 8 nibbles) +