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Difference between revisions of "intel/xeon e7/e7-2803"
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{{intel title|Xeon E7-2803}} | {{intel title|Xeon E7-2803}} | ||
| − | {{ | + | {{chip |
| name = Xeon E7-2803 | | name = Xeon E7-2803 | ||
| no image = Yes | | no image = Yes | ||
| Line 10: | Line 10: | ||
| model number = E7-2803 | | model number = E7-2803 | ||
| part number = AT80615006438AB | | part number = AT80615006438AB | ||
| − | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
| + | | part number 4 = | ||
| market = Server | | market = Server | ||
| first announced = April 5, 2011 | | first announced = April 5, 2011 | ||
| Line 18: | Line 18: | ||
| last order = August 21, 2015 | | last order = August 21, 2015 | ||
| last shipment = February 2, 2018 | | last shipment = February 2, 2018 | ||
| + | | release price = $774.00 | ||
| family = Xeon E7 | | family = Xeon E7 | ||
| Line 33: | Line 34: | ||
| microarch = Westmere | | microarch = Westmere | ||
| − | | platform = | + | | platform = Boxboro |
| chipset = Boxboro | | chipset = Boxboro | ||
| core name = Westmere EX | | core name = Westmere EX | ||
| Line 47: | Line 48: | ||
| thread count = 12 | | thread count = 12 | ||
| max cpus = 2 | | max cpus = 2 | ||
| − | | max memory = 1 | + | | max memory = 1 TiB |
| + | |||
| − | |||
| v core = 1.35 V | | v core = 1.35 V | ||
| v core tolerance = | | v core tolerance = | ||
| Line 67: | Line 68: | ||
| tstorage max = 85 °C | | tstorage max = 85 °C | ||
| − | + | | package module 1 = {{packages/intel/lga-1567}} | |
| − | |||
| − | |||
| − | |||
| − | | package | ||
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| − | |||
| − | |||
| − | |||
| − | |||
}} | }} | ||
'''Xeon E7-2803''' is a {{arch|64}} hexa-core [[x86]] data center microprocessor that supports up to 2 sockets. This first generation ({{intel|Westmere|Westmere}}-based) {{intel|Xeon E7}} processor operates at 1.73 GHz with a TDP of 105 W but does not support {{intel|turbo boost technology}}. This processor supports up to 4 channels of DDR3, supporting up to 1 TB of memory. | '''Xeon E7-2803''' is a {{arch|64}} hexa-core [[x86]] data center microprocessor that supports up to 2 sockets. This first generation ({{intel|Westmere|Westmere}}-based) {{intel|Xeon E7}} processor operates at 1.73 GHz with a TDP of 105 W but does not support {{intel|turbo boost technology}}. This processor supports up to 4 channels of DDR3, supporting up to 1 TB of memory. | ||
| Line 82: | Line 74: | ||
== Cache == | == Cache == | ||
{{main|intel/microarchitectures/westmere#Memory_Hierarchy|l1=Westmere § Cache}} | {{main|intel/microarchitectures/westmere#Memory_Hierarchy|l1=Westmere § Cache}} | ||
| − | {{cache | + | {{cache size |
| − | |l1i cache=192 | + | |l1 cache = 384 KiB |
| − | |l1i break=6x32 | + | |l1i cache=192 KiB |
| + | |l1i break=6x32 KiB | ||
|l1i desc=4-way set associative | |l1i desc=4-way set associative | ||
| − | |l1i | + | |l1i policy=write-back |
| − | |l1d cache=192 | + | |l1d cache=192 KiB |
| − | |l1d break=6x32 | + | |l1d break=6x32 KiB |
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
| − | |l1d | + | |l1d policy=write-back |
| − | |l2 cache=1.5 | + | |l2 cache=1.5 MiB |
| − | |l2 break=6x256 | + | |l2 break=6x256 KiB |
|l2 desc=8-way set associative | |l2 desc=8-way set associative | ||
| − | |l2 | + | |l2 policy=write-back |
| − | |l3 cache=18 | + | |l3 cache=18 MiB |
| − | |l3 break= | + | |l3 break=6x3 MiB |
|l3 desc=16-way set associative | |l3 desc=16-way set associative | ||
| − | |l3 | + | |l3 policy=write-back |
}} | }} | ||
| Line 105: | Line 98: | ||
== Memory controller == | == Memory controller == | ||
| − | {{ | + | {{memory controller |
| − | | type | + | |type=DDR3-800 |
| − | | controllers | + | |ecc=Yes |
| − | | channels | + | |max mem=1 TiB |
| − | | | + | |controllers=1 |
| − | | | + | |channels=4 |
| − | | bandwidth | + | |max bandwidth=23.84 GiB/s |
| − | | bandwidth | + | |bandwidth schan=5.96 GiB/s |
| − | | | + | |bandwidth dchan=11.92 GiB/s |
| + | |bandwidth tchan=17.88 GiB/s | ||
| + | |bandwidth qchan=23.84 GiB/s | ||
}} | }} | ||
| − | == Features == | + | == Features == |
| − | {{ | + | {{x86 features |
| − | | | + | |real=Yes |
| − | | | + | |protected=Yes |
| − | | | + | |smm=Yes |
| − | | | + | |fpu=Yes |
| − | | | + | |x8616=Yes |
| − | | | + | |x8632=Yes |
| − | | | + | |x8664=Yes |
| − | | | + | |nx=Yes |
| − | | | + | |3dnow=No |
| − | | | + | |e3dnow=No |
| − | | | + | |mmx=Yes |
| − | + | |emmx=Yes | |
| − | | | + | |sse=Yes |
| − | | sse | + | |sse2=Yes |
| − | | sse2 | + | |sse3=Yes |
| − | | sse3 | + | |ssse3=Yes |
| − | | ssse3 | + | |sse41=Yes |
| − | | | + | |sse42=Yes |
| − | | | + | |sse4a=No |
| − | | | + | |avx=No |
| − | | | + | |avx2=No |
| − | | | + | |
| − | | | + | |abm=No |
| − | | | + | |tbm=No |
| − | | bmi1 | + | |bmi1=No |
| − | | bmi2 | + | |bmi2=No |
| − | | f16c | + | |fma3=No |
| − | | | + | |fma4=No |
| − | | mpx | + | |aes=Yes |
| − | | sgx | + | |rdrand=No |
| − | | | + | |sha=No |
| − | | | + | |xop=No |
| − | | | + | |adx=No |
| − | | | + | |clmul=No |
| + | |f16c=No | ||
| + | |tbt1=No | ||
| + | |tbt2=No | ||
| + | |tbmt3=No | ||
| + | |bpt=No | ||
| + | |eist=Yes | ||
| + | |flex=No | ||
| + | |fastmem=No | ||
| + | |isrt=No | ||
| + | |mwt=No | ||
| + | |sipp=No | ||
| + | |att=No | ||
| + | |ipt=No | ||
| + | |tsx=No | ||
| + | |txt=Yes | ||
| + | |ht=Yes | ||
| + | |vpro=No | ||
| + | |vtx=Yes | ||
| + | |vtd=Yes | ||
| + | |ept=Yes | ||
| + | |mpx=No | ||
| + | |sgx=No | ||
| + | |securekey=No | ||
| + | |osguard=No | ||
| + | |smartmp=No | ||
| + | |powernow=No | ||
| + | |amdv=No | ||
| + | |rvi=No | ||
}} | }} | ||
Latest revision as of 15:28, 13 December 2017
| Edit Values | ||||||||||||
| Xeon E7-2803 | ||||||||||||
| General Info | ||||||||||||
| Designer | Intel | |||||||||||
| Manufacturer | Intel | |||||||||||
| Model Number | E7-2803 | |||||||||||
| Part Number | AT80615006438AB | |||||||||||
| S-Spec | SLC3M | |||||||||||
| Market | Server | |||||||||||
| Introduction | April 5, 2011 (announced) April 5, 2011 (launched) | |||||||||||
| End-of-life | August 21, 2015 (last order) February 2, 2018 (last shipment) | |||||||||||
| Release Price | $774.00 | |||||||||||
| Shop | Amazon | |||||||||||
| General Specs | ||||||||||||
| Family | Xeon E7 | |||||||||||
| Series | E7-2800 | |||||||||||
| Locked | Yes | |||||||||||
| Frequency | 1733.33 MHz | |||||||||||
| Bus type | QPI | |||||||||||
| Bus rate | 4.80 GT/s | |||||||||||
| Clock multiplier | 13 | |||||||||||
| CPUID | 206F2 | |||||||||||
| Microarchitecture | ||||||||||||
| Microarchitecture | Westmere | |||||||||||
| Platform | Boxboro | |||||||||||
| Chipset | Boxboro | |||||||||||
| Core Name | Westmere EX | |||||||||||
| Core Family | 6 | |||||||||||
| Core Model | 47 | |||||||||||
| Core Stepping | A2 | |||||||||||
| Process | 32 nm | |||||||||||
| Transistors | 2,600,000,000 | |||||||||||
| Technology | CMOS | |||||||||||
| Die | 513 mm² | |||||||||||
| Word Size | 64 bit | |||||||||||
| Cores | 6 | |||||||||||
| Threads | 12 | |||||||||||
| Max Memory | 1 TiB | |||||||||||
| Multiprocessing | ||||||||||||
| Max SMP | 2-Way (Multiprocessor) | |||||||||||
| Electrical | ||||||||||||
| Vcore | 1.35 V | |||||||||||
| TDP | 105 W | |||||||||||
| Tcase | 5 °C – 64 °C | |||||||||||
| Tstorage | -40 °C – 85 °C | |||||||||||
| Packaging | ||||||||||||
| ||||||||||||
Xeon E7-2803 is a 64-bit hexa-core x86 data center microprocessor that supports up to 2 sockets. This first generation (Westmere-based) Xeon E7 processor operates at 1.73 GHz with a TDP of 105 W but does not support turbo boost technology. This processor supports up to 4 channels of DDR3, supporting up to 1 TB of memory.
Contents
Cache[edit]
- Main article: Westmere § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Graphics[edit]
This SoC has no integrated graphics processing unit.
Memory controller[edit]
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Integrated Memory Controller
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Features[edit]
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Facts about "Xeon E7-2803 - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon E7-2803 - Intel#package + |
| base frequency | 1,733.33 MHz (1.733 GHz, 1,733,330 kHz) + |
| bus rate | 4,800 MT/s (4.8 GT/s, 4,800,000 kT/s) + |
| bus type | QPI + |
| chipset | Boxboro + |
| clock multiplier | 13 + |
| core count | 6 + |
| core family | 6 + |
| core model | 47 + |
| core name | Westmere EX + |
| core stepping | A2 + |
| core voltage | 1.35 V (13.5 dV, 135 cV, 1,350 mV) + |
| cpuid | 206F2 + |
| designer | Intel + |
| die area | 513 mm² (0.795 in², 5.13 cm², 513,000,000 µm²) + |
| family | Xeon E7 + |
| first announced | April 5, 2011 + |
| first launched | April 5, 2011 + |
| full page name | intel/xeon e7/e7-2803 + |
| has ecc memory support | true + |
| has extended page tables support | true + |
| has feature | Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel VT-x +, Intel VT-d + and Extended Page Tables + |
| has intel enhanced speedstep technology | true + |
| has intel trusted execution technology | true + |
| has intel vt-d technology | true + |
| has intel vt-x technology | true + |
| has locked clock multiplier | true + |
| has second level address translation support | true + |
| has simultaneous multithreading | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| instance of | microprocessor + |
| l1$ size | 384 KiB (393,216 B, 0.375 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 192 KiB (196,608 B, 0.188 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 192 KiB (196,608 B, 0.188 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) + |
| last order | August 21, 2015 + |
| last shipment | February 2, 2018 + |
| ldate | April 5, 2011 + |
| manufacturer | Intel + |
| market segment | Server + |
| max case temperature | 337.15 K (64 °C, 147.2 °F, 606.87 °R) + |
| max cpu count | 2 + |
| max memory | 1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) + |
| max memory bandwidth | 23.84 GiB/s (24,412.16 MiB/s, 25.598 GB/s, 25,598.005 MB/s, 0.0233 TiB/s, 0.0256 TB/s) + |
| max memory channels | 4 + |
| max storage temperature | 358.15 K (85 °C, 185 °F, 644.67 °R) + |
| microarchitecture | Westmere + |
| min case temperature | 278.15 K (5 °C, 41 °F, 500.67 °R) + |
| min storage temperature | 233.15 K (-40 °C, -40 °F, 419.67 °R) + |
| model number | E7-2803 + |
| name | Xeon E7-2803 + |
| package | FCLGA-8 + |
| part number | AT80615006438AB + |
| platform | Boxboro + |
| process | 32 nm (0.032 μm, 3.2e-5 mm) + |
| release price | $ 774.00 (€ 696.60, £ 626.94, ¥ 79,977.42) + |
| s-spec | SLC3M + |
| series | E7-2800 + |
| smp max ways | 2 + |
| supported memory type | DDR3-800 + |
| tdp | 105 W (105,000 mW, 0.141 hp, 0.105 kW) + |
| technology | CMOS + |
| thread count | 12 + |
| transistor count | 2,600,000,000 + |
| word size | 64 bit (8 octets, 16 nibbles) + |