From WikiChip
Difference between revisions of "intel/xeon e5/e5-2699r v4"
< intel‎ | xeon e5

(Created page with "{{intel title|Xeon E5-2699R v4}} {{mpu | name = Xeon E5-2699R v4 | no image = Yes | image = | image size = | caption...")
 
m (Bot: moving all {{mpu}} to {{chip}})
 
(6 intermediate revisions by 2 users not shown)
Line 1: Line 1:
 
{{intel title|Xeon E5-2699R v4}}
 
{{intel title|Xeon E5-2699R v4}}
−
{{mpu
+
{{chip
 
| name                = Xeon E5-2699R v4
 
| name                = Xeon E5-2699R v4
 
| no image            = Yes
 
| no image            = Yes
Line 10: Line 10:
 
| model number        = E5-2699R v4
 
| model number        = E5-2699R v4
 
| part number        = CM8066003216500
 
| part number        = CM8066003216500
−
| part number 1      =
 
 
| part number 2      =  
 
| part number 2      =  
 
| part number 3      =  
 
| part number 3      =  
 +
| part number 4      =
 
| market              = Embedded
 
| market              = Embedded
−
| first announced    = June 20, 2016
+
| first announced    = October 25, 2016
−
| first launched      = June 20, 2016
+
| first launched      = October 25, 2016
 
| last order          =  
 
| last order          =  
 
| last shipment      =  
 
| last shipment      =  
Line 54: Line 54:
 
| max memory          = 1,536 GiB
 
| max memory          = 1,536 GiB
  
−
| electrical          = Yes
+
 
 
| v core              = 1.82 V
 
| v core              = 1.82 V
 
| v core tolerance    =  
 
| v core tolerance    =  
Line 82: Line 82:
 
| socket 0            = LGA-2011-v3
 
| socket 0            = LGA-2011-v3
 
| socket 0 type      = LGA
 
| socket 0 type      = LGA
 +
}}
 +
The '''Xeon E5-2699R v4''' is a {{arch|64}} [[docosa-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This embedded server MPU is designed for low-power 2S environments. Operating at 2.2 GHz with a {{intel|turbo boost}} frequency of 3.6 GHz for a single active core, this MPU has a TDP of 145 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
 +
 +
== Cache ==
 +
{{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}}
 +
{{cache info
 +
|l1i cache=704 KiB
 +
|l1i break=22x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1i extra=(per core, write-back)
 +
|l1d cache=704 KiB
 +
|l1d break=22x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d extra=(per core, write-back)
 +
|l2 cache=5.5 MiB
 +
|l2 break=22x256 KiB
 +
|l2 desc=8-way set associative
 +
|l2 extra=(per core, write-back)
 +
|l3 cache=55 MiB
 +
|l3 break=22x2.5 MiB
 +
|l3 desc=20-way set associative
 +
|l3 extra=(shared, per core, write-back)
 +
}}
 +
 +
== Graphics ==
 +
This microprocessor has no [[integrated graphics processing unit]].
 +
 +
== Memory controller ==
 +
{{integrated memory controller
 +
| type              = DDR4-2400
 +
| controllers        = 1
 +
| channels          = 4
 +
| ecc support        = Yes
 +
| max bandwidth      = 71.53 GiB/s
 +
| bandwidth schan    = 17.88 GiB/s
 +
| bandwidth dchan    = 35.76 GiB/s
 +
| max memory        = 1,536 GiB
 +
| pae                = 46 bit
 +
}}
 +
 +
== Expansions ==
 +
{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 40
 +
| pcie config        = x4
 +
| pcie config 1      = x8
 +
| pcie config 2      = x16
 +
}}
 +
 +
== Features ==
 +
{{x86 features
 +
| em64t      = Yes
 +
| nx          = Yes
 +
| txt        = Yes
 +
| tsx        = Yes
 +
| vpro        = Yes
 +
| ht          = Yes
 +
| tbt1        =
 +
| tbt2        = Yes
 +
| tbmt3      =
 +
| bpt        =
 +
| vt-x        = Yes
 +
| vt-d        = Yes
 +
| ept        = Yes
 +
| mmx        = Yes
 +
| sse        = Yes
 +
| sse2        = Yes
 +
| sse3        = Yes
 +
| ssse3      = Yes
 +
| sse4.1      = Yes
 +
| sse4.2      = Yes
 +
| aes        = Yes
 +
| pclmul      = Yes
 +
| avx        = Yes
 +
| avx2        = Yes
 +
| bmi        = Yes
 +
| bmi1        = Yes
 +
| bmi2        = Yes
 +
| f16c        = Yes
 +
| fma3        = Yes
 +
| mpx        =
 +
| sgx        =
 +
| eist        = Yes
 +
| secure key  = Yes
 +
| os guard    = Yes
 +
| intel at    =
 +
| intel ipt  =
 
}}
 
}}

Latest revision as of 15:28, 13 December 2017

Edit Values
Xeon E5-2699R v4
General Info
DesignerIntel
ManufacturerIntel
Model NumberE5-2699R v4
Part NumberCM8066003216500
S-SpecSR31X
MarketEmbedded
IntroductionOctober 25, 2016 (announced)
October 25, 2016 (launched)
Release Price$4560
ShopAmazon
General Specs
FamilyXeon E5
SeriesE5-2000
LockedYes
Frequency2,200 MHz
Turbo FrequencyYes
Turbo Frequency3,600 MHz (1 core)
Bus typeQPI
Bus speed4,800 MHz
Bus rate2 × 9.6 GT/s
Clock multiplier22
CPUID406F1
Microarchitecture
MicroarchitectureBroadwell
PlatformGrantley EP 2S
ChipsetC610 Series
Core NameBroadwell EP
Core Family6
Core Model4F
Core SteppingB0
Process14 nm
Transistors7,200,000,000
TechnologyCMOS
Die456.12 mm²
Word Size64 bit
Cores22
Threads44
Max Memory1,536 GiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
Vcore1.82 V
VI/O1.2 V ± 3%
TDP145 W
Tcase0 °C – ? °C
Tstorage-25 °C – 125 °C

The Xeon E5-2699R v4 is a 64-bit docosa-core x86 microprocessor introduced by Intel in 2016. This embedded server MPU is designed for low-power 2S environments. Operating at 2.2 GHz with a turbo boost frequency of 3.6 GHz for a single active core, this MPU has a TDP of 145 W and is manufactured on a 14 nm process (based on Broadwell).

Cache[edit]

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 704 KiB
720,896 B
0.688 MiB
22x32 KiB 8-way set associative (per core, write-back)
L1D$ 704 KiB
720,896 B
0.688 MiB
22x32 KiB 8-way set associative (per core, write-back)
L2$ 5.5 MiB
5,632 KiB
5,767,168 B
0.00537 GiB
22x256 KiB 8-way set associative (per core, write-back)
L3$ 55 MiB
56,320 KiB
57,671,680 B
0.0537 GiB
22x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics[edit]

This microprocessor has no integrated graphics processing unit.

Memory controller[edit]

Integrated Memory Controller
Type DDR4-2400
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 71.53 GiB/s
Bandwidth (single) 17.88 GiB/s
Bandwidth (dual) 35.76 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes40
Configsx4, x16


Features[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e5/e5-2699r_v4&oldid=71014"
Facts about "Xeon E5-2699R v4 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon E5-2699R v4 - Intel#io +
base frequency2,200 MHz (2.2 GHz, 2,200,000 kHz) +
bus links2 +
bus rate9,600 MT/s (9.6 GT/s, 9,600,000 kT/s) +
bus speed4,800 MHz (4.8 GHz, 4,800,000 kHz) +
bus typeQPI +
chipsetC610 Series +
clock multiplier22 +
core count22 +
core family6 +
core model4F +
core nameBroadwell EP +
core steppingB0 +
core voltage1.82 V (18.2 dV, 182 cV, 1,820 mV) +
cpuid406F1 +
designerIntel +
die area456.12 mm² (0.707 in², 4.561 cm², 456,120,000 µm²) +
familyXeon E5 +
first announcedOctober 25, 2016 +
first launchedOctober 25, 2016 +
full page nameintel/xeon e5/e5-2699r v4 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
io voltage1.2 V (12 dV, 120 cV, 1,200 mV) +
io voltage tolerance3% +
l1d$ description8-way set associative +
l1d$ size704 KiB (720,896 B, 0.688 MiB) +
l1i$ description8-way set associative +
l1i$ size704 KiB (720,896 B, 0.688 MiB) +
l2$ description8-way set associative +
l2$ size5.5 MiB (5,632 KiB, 5,767,168 B, 0.00537 GiB) +
l3$ description20-way set associative +
l3$ size55 MiB (56,320 KiB, 57,671,680 B, 0.0537 GiB) +
ldateOctober 25, 2016 +
manufacturerIntel +
market segmentEmbedded +
max cpu count2 +
max memory1,572,864 MiB (1,610,612,736 KiB, 1,649,267,441,664 B, 1,536 GiB, 1.5 TiB) +
max pcie lanes40 +
max storage temperature398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitectureBroadwell +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature248.15 K (-25 °C, -13 °F, 446.67 °R) +
model numberE5-2699R v4 +
nameXeon E5-2699R v4 +
part numberCM8066003216500 +
platformGrantley EP 2S +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 4,560.00 (€ 4,104.00, £ 3,693.60, ¥ 471,184.80) +
s-specSR31X +
seriesE5-2000 +
smp max ways2 +
tdp145 W (145,000 mW, 0.194 hp, 0.145 kW) +
technologyCMOS +
thread count44 +
transistor count7,200,000,000 +
turbo frequency (1 core)3,600 MHz (3.6 GHz, 3,600,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +