Semiconductor & Computer Engineering
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Difference between revisions of "intel/mobile pentium ii/300"
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{{intel title|Mobile Pentium II 300}} | {{intel title|Mobile Pentium II 300}} | ||
| − | {{ | + | {{chip |
| name = Mobile Pentium II 300 | | name = Mobile Pentium II 300 | ||
| no image = Yes | | no image = Yes | ||
| Line 10: | Line 10: | ||
| model number = 300 | | model number = 300 | ||
| part number = 80523TX300512 | | part number = 80523TX300512 | ||
| − | | part number | + | | part number 2 = PMD30005002AA |
| − | | part number | + | | part number 3 = PME30005002AA |
| − | | part number | + | | part number 4 = PME30005001AA |
| market = Mobile | | market = Mobile | ||
| first announced = 1998 | | first announced = 1998 | ||
| Line 49: | Line 49: | ||
| thread count = 1 | | thread count = 1 | ||
| max cpus = 1 | | max cpus = 1 | ||
| − | | max memory = 64 | + | | max memory = 64 GiB |
| + | |||
| − | |||
| power = | | power = | ||
| v core = 1.6 | | v core = 1.6 | ||
| Line 73: | Line 73: | ||
== Cache == | == Cache == | ||
| − | {{main|intel/microarchitectures/p6#Memory_Hierarchy|l1=P6 | + | {{main|intel/microarchitectures/p6#Memory_Hierarchy|l1=P6 § Cache}} |
{{cache info | {{cache info | ||
| − | |l1i cache=16 | + | |l1i cache=16 KiB |
| − | |l1i break=1x16 | + | |l1i break=1x16 KiB |
|l1i desc=4-way set associative | |l1i desc=4-way set associative | ||
|l1i extra= | |l1i extra= | ||
| − | |l1d cache=16 | + | |l1d cache=16 KiB |
| − | |l1d break=1x16 | + | |l1d break=1x16 KiB |
|l1d desc=4-way set associative | |l1d desc=4-way set associative | ||
|l1d extra= | |l1d extra= | ||
| − | |l2 cache=512 | + | |l2 cache=512 KiB |
| − | |l2 break=1x512 | + | |l2 break=1x512 KiB |
|l2 desc=4-way set associative | |l2 desc=4-way set associative | ||
|l2 extra=(separate die, same package) | |l2 extra=(separate die, same package) | ||
| Line 100: | Line 100: | ||
== Features == | == Features == | ||
| − | {{ | + | {{x86 features |
| mmx = Yes | | mmx = Yes | ||
}} | }} | ||
Latest revision as of 15:25, 13 December 2017
| Edit Values | |
| Mobile Pentium II 300 | |
| General Info | |
| Designer | Intel |
| Manufacturer | Intel |
| Model Number | 300 |
| Part Number | 80523TX300512, PMD30005002AA, PME30005002AA, PME30005001AA |
| S-Spec | SL2RS, SL2Y7 |
| Market | Mobile |
| Introduction | 1998 (announced) September 9, 1998 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | Mobile Pentium II |
| Locked | Yes |
| Frequency | 300 MHz |
| Bus type | FSB |
| Bus speed | 66 MHz |
| Clock multiplier | 4.5 |
| CPUID | 0652h |
| Microarchitecture | |
| Microarchitecture | P6 |
| Core Name | Tonga |
| Core Family | 6 |
| Core Model | 5 |
| Core Stepping | mdA0, mdB0, mdB0 |
| Process | 250 nm |
| Transistors | 7,500,000 |
| Technology | CMOS |
| Die | 131 mm² |
| Word Size | 32 bit |
| Cores | 1 |
| Threads | 1 |
| Max Memory | 64 GiB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Vcore | 1.6 ± 0.12 V |
| TDP | 11.1 W |
| OP Temperature | -40 °C – 85 °C |
The Mobile Pentium II 300 was a 32-bit x86 microprocessor, part of the first batch from the Mobile Pentium II family. This MPU operated at 300 MHz and had a TDP of 11.1 Watts. This chip was manufactured in 250 nm process and included a larger 512 KB of L2$ on package, but on a separate die.
Contents
Cache[edit]
- Main article: P6 § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 16 KiB 16,384 B 0.0156 MiB |
1x16 KiB 4-way set associative |
| L1D$ | 16 KiB 16,384 B 0.0156 MiB |
1x16 KiB 4-way set associative |
| L2$ | 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB |
1x512 KiB 4-way set associative (separate die, same package) |
Graphics[edit]
This processor has no integrated graphics processing unit.
Memory controller[edit]
This processor has no integrated memory controller.
Features[edit]
[Edit/Modify Supported Features]
 |
Supported x86 Extensions & Processor Features
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Facts about "Mobile Pentium II 300 - Intel"
| base frequency | 300 MHz (0.3 GHz, 300,000 kHz) + |
| bus speed | 66 MHz (0.066 GHz, 66,000 kHz) + |
| bus type | FSB + |
| clock multiplier | 4.5 + |
| core count | 1 + |
| core family | 6 + |
| core model | 5 + |
| core name | Tonga + |
| core stepping | mdA0 + and mdB0 + |
| core voltage | 1.6 V (16 dV, 160 cV, 1,600 mV) + |
| core voltage tolerance | 0.12 V + |
| cpuid | 0652h + |
| designer | Intel + |
| die area | 131 mm² (0.203 in², 1.31 cm², 131,000,000 µm²) + |
| family | Mobile Pentium II + |
| first announced | 1998 + |
| first launched | September 9, 1998 + |
| full page name | intel/mobile pentium ii/300 + |
| has locked clock multiplier | true + |
| instance of | microprocessor + |
| l1d$ description | 4-way set associative + |
| l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
| ldate | September 9, 1998 + |
| manufacturer | Intel + |
| market segment | Mobile + |
| max cpu count | 1 + |
| max memory | 65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) + |
| max operating temperature | 85 °C + |
| microarchitecture | P6 + |
| min operating temperature | -40 °C + |
| model number | 300 + |
| name | Mobile Pentium II 300 + |
| part number | 80523TX300512 +, PMD30005002AA +, PME30005002AA + and PME30005001AA + |
| process | 250 nm (0.25 μm, 2.5e-4 mm) + |
| s-spec | SL2RS + and SL2Y7 + |
| smp max ways | 1 + |
| tdp | 11.1 W (11,100 mW, 0.0149 hp, 0.0111 kW) + |
| technology | CMOS + |
| thread count | 1 + |
| transistor count | 7,500,000 + |
| word size | 32 bit (4 octets, 8 nibbles) + |