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Difference between revisions of "intel/core i5/i5-6260u"
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{{intel title|Core i5-6260U}} | {{intel title|Core i5-6260U}} | ||
− | {{ | + | {{chip |
|name=Core i5-6260U | |name=Core i5-6260U | ||
− | |image=skylake ( | + | |image=skylake u (front; iris).png |
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|model number=i5-6260U | |model number=i5-6260U | ||
+ | |part number=FJ8066202496511 | ||
|s-spec=SR2JC | |s-spec=SR2JC | ||
|market=Mobile | |market=Mobile | ||
+ | |first announced=September 1, 2015 | ||
+ | |first launched=September 27, 2015 | ||
+ | |release price=$304.00 | ||
|family=Core i5 | |family=Core i5 | ||
|series=i5-6000 | |series=i5-6000 | ||
Line 13: | Line 17: | ||
|frequency=1,800 MHz | |frequency=1,800 MHz | ||
|turbo frequency1=2,900 MHz | |turbo frequency1=2,900 MHz | ||
+ | |turbo frequency2=2,700 MHz | ||
|bus type=OPI | |bus type=OPI | ||
|bus rate=4 GT/s | |bus rate=4 GT/s | ||
Line 26: | Line 31: | ||
|technology=CMOS | |technology=CMOS | ||
|mcp=Yes | |mcp=Yes | ||
− | |die count= | + | |die count=3 |
|word size=64 bit | |word size=64 bit | ||
|core count=2 | |core count=2 | ||
Line 42: | Line 47: | ||
|package module 1={{packages/intel/fcbga-1356}} | |package module 1={{packages/intel/fcbga-1356}} | ||
}} | }} | ||
− | '''Core i5-6260U''' is a {{arch|64}} [[dual-core]] mid-range performance [[x86]] mobile microprocessor introduced by [[Intel]] in late [[2015]]. Fabricated on a [[14 nm process]] based on the {{intel|Skylake}} microarchitecture, this processor operates at 1.8 GHz with a {{intel|turbo boost}} of up to 2.9 GHz. The i5-6260U has a TDP of 15 W with a configurable-down | + | '''Core i5-6260U''' is a {{arch|64}} [[dual-core]] mid-range performance [[x86]] mobile microprocessor introduced by [[Intel]] in late [[2015]]. Fabricated on a [[14 nm process]] based on the {{intel|Skylake}} microarchitecture, this processor operates at 1.8 GHz with a {{intel|turbo boost}} of up to 2.9 GHz. The i5-6260U has a TDP of 15 W with a configurable TDP-down of 9.5 W. This chip incorporates the {{intel|Iris Graphics 540}} GPU operating at 300 MHz with a burst frequency of 950 MHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory. The 6260U comes with an additional 64 MiB of [[embedded DRAM]] side cache. |
== Cache == | == Cache == | ||
Line 62: | Line 67: | ||
|l3 break=2x2 MiB | |l3 break=2x2 MiB | ||
|l3 policy=write-back | |l3 policy=write-back | ||
+ | |l4 cache=64 MiB | ||
}} | }} | ||
Line 89: | Line 95: | ||
== Graphics == | == Graphics == | ||
− | The Iris | + | The Iris Graphics 540 includes 64 MiB of side eDRAM cache in addition to everything else. |
{{integrated graphics | {{integrated graphics | ||
− | | gpu = Iris | + | | gpu = Iris Graphics 540 |
| device id = 0x1926 | | device id = 0x1926 | ||
| designer = Intel | | designer = Intel | ||
Line 156: | Line 162: | ||
|avx=Yes | |avx=Yes | ||
|avx2=Yes | |avx2=Yes | ||
− | + | ||
|abm=Yes | |abm=Yes | ||
|tbm=No | |tbm=No |
Latest revision as of 15:20, 13 December 2017
Edit Values | |||||||||||||
Core i5-6260U | |||||||||||||
General Info | |||||||||||||
Designer | Intel | ||||||||||||
Manufacturer | Intel | ||||||||||||
Model Number | i5-6260U | ||||||||||||
Part Number | FJ8066202496511 | ||||||||||||
S-Spec | SR2JC | ||||||||||||
Market | Mobile | ||||||||||||
Introduction | September 1, 2015 (announced) September 27, 2015 (launched) | ||||||||||||
Release Price | $304.00 | ||||||||||||
Shop | Amazon | ||||||||||||
General Specs | |||||||||||||
Family | Core i5 | ||||||||||||
Series | i5-6000 | ||||||||||||
Locked | Yes | ||||||||||||
Frequency | 1,800 MHz | ||||||||||||
Turbo Frequency | 2,900 MHz (1 core), 2,700 MHz (2 cores) | ||||||||||||
Bus type | OPI | ||||||||||||
Bus rate | 4 GT/s | ||||||||||||
Clock multiplier | 18 | ||||||||||||
Microarchitecture | |||||||||||||
ISA | x86-64 (x86) | ||||||||||||
Microarchitecture | Skylake | ||||||||||||
Core Name | Skylake U | ||||||||||||
Core Family | 6 | ||||||||||||
Core Model | 78 | ||||||||||||
Core Stepping | K1 | ||||||||||||
Process | 14 nm | ||||||||||||
Technology | CMOS | ||||||||||||
MCP | Yes (3 dies) | ||||||||||||
Word Size | 64 bit | ||||||||||||
Cores | 2 | ||||||||||||
Threads | 4 | ||||||||||||
Max Memory | 32 GiB | ||||||||||||
Multiprocessing | |||||||||||||
Max SMP | 1-Way (Uniprocessor) | ||||||||||||
Electrical | |||||||||||||
Vcore | 0.55 V-1.52 V | ||||||||||||
TDP | 15 W | ||||||||||||
cTDP down | 9.5 W | ||||||||||||
Tjunction | 0 °C – 100 °C | ||||||||||||
Tstorage | -25 °C – 125 °C | ||||||||||||
Packaging | |||||||||||||
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Core i5-6260U is a 64-bit dual-core mid-range performance x86 mobile microprocessor introduced by Intel in late 2015. Fabricated on a 14 nm process based on the Skylake microarchitecture, this processor operates at 1.8 GHz with a turbo boost of up to 2.9 GHz. The i5-6260U has a TDP of 15 W with a configurable TDP-down of 9.5 W. This chip incorporates the Iris Graphics 540 GPU operating at 300 MHz with a burst frequency of 950 MHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory. The 6260U comes with an additional 64 MiB of embedded DRAM side cache.
Cache[edit]
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options
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Graphics[edit]
The Iris Graphics 540 includes 64 MiB of side eDRAM cache in addition to everything else.
Integrated Graphics Information
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[Edit] Skylake (Gen9) Hardware Accelerated Video Capabilities | |||||||
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Codec | Encode | Decode | |||||
Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
MPEG-2 (H.262) | Main | High | 1080p (FHD) | Main | Main, High | 1080p (FHD) | |
MPEG-4 AVC (H.264) | High, Main | 5.1 | 2160p (4K) | Main, High, SHP, MHP | 5.1 | 2160p (4K) | |
JPEG/MJPEG | Baseline | - | 16k x 16k | Baseline | Unified | 16k x 16k | |
HEVC (H.265) | Main | 5.1 | 2160p (4K) | Main, Main 10 | 5.1 | 2160p (4K) | |
VC-1 | ✘ | Advanced, Main, Simple | 3, High | 3840x3840 | |||
VP8 | Unified | Unified | - | 0 | Unified | 1080p | |
VP9 | ✘ | 0 | Unified | 2160p (4K) |
Features[edit]
[Edit/Modify Supported Features]
Facts about "Core i5-6260U - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i5-6260U - Intel#package + and Core i5-6260U - Intel#io + |
base frequency | 1,800 MHz (1.8 GHz, 1,800,000 kHz) + |
bus rate | 4,000 MT/s (4 GT/s, 4,000,000 kT/s) + |
bus type | OPI + |
clock multiplier | 18 + |
core count | 2 + |
core family | 6 + |
core model | 78 + |
core name | Skylake U + |
core stepping | K1 + |
core voltage (max) | 1.52 V (15.2 dV, 152 cV, 1,520 mV) + |
core voltage (min) | 0.55 V (5.5 dV, 55 cV, 550 mV) + |
designer | Intel + |
device id | 0x1926 + |
die count | 3 + |
family | Core i5 + |
first announced | September 1, 2015 + |
first launched | September 27, 2015 + |
full page name | intel/core i5/i5-6260u + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has ecc memory support | false + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard +, Flex Memory Access +, Smart Response Technology +, My WiFi Technology + and Identity Protection Technology + |
has intel enhanced speedstep technology | true + |
has intel flex memory access support | true + |
has intel identity protection technology support | true + |
has intel my wifi technology support | true + |
has intel secure key technology | true + |
has intel smart response technology support | true + |
has intel supervisor mode execution protection | true + |
has intel turbo boost technology 2 0 | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
integrated gpu | Iris Graphics 540 + |
integrated gpu base frequency | 300 MHz (0.3 GHz, 300,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 48 + |
integrated gpu max frequency | 950 MHz (0.95 GHz, 950,000 KHz) + |
integrated gpu max memory | 32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB) + |
is multi-chip package | true + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
l4$ size | 64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) + |
ldate | September 27, 2015 + |
main image | + |
manufacturer | Intel + |
market segment | Mobile + |
max cpu count | 1 + |
max junction temperature | 373.15 K (100 °C, 212 °F, 671.67 °R) + |
max memory | 32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB, 0.0313 TiB) + |
max memory bandwidth | 31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 12 + |
max storage temperature | 398.15 K (125 °C, 257 °F, 716.67 °R) + |
microarchitecture | Skylake + |
min junction temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min storage temperature | 248.15 K (-25 °C, -13 °F, 446.67 °R) + |
model number | i5-6260U + |
name | Core i5-6260U + |
package | FCBGA-1356 + |
part number | FJ8066202496511 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 304.00 (€ 273.60, £ 246.24, ¥ 31,412.32) + |
s-spec | SR2JC + |
series | i5-6000 + |
smp max ways | 1 + |
supported memory type | DDR4-2133 +, LPDDR3-1866 + and DDR3L-1600 + |
tdp | 15 W (15,000 mW, 0.0201 hp, 0.015 kW) + |
tdp down | 9.5 W (9,500 mW, 0.0127 hp, 0.0095 kW) + |
technology | CMOS + |
thread count | 4 + |
turbo frequency (1 core) | 2,900 MHz (2.9 GHz, 2,900,000 kHz) + |
turbo frequency (2 cores) | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |
x86/has memory protection extensions | true + |
x86/has software guard extensions | true + |