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Difference between revisions of "intel/celeron/p4600"
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{{intel title|Celeron P4600}} | {{intel title|Celeron P4600}} | ||
− | {{ | + | {{chip |
| name = Intel Celeron P4600 | | name = Intel Celeron P4600 | ||
| no image = yes | | no image = yes | ||
Line 30: | Line 30: | ||
| s-spec qs = | | s-spec qs = | ||
| cpuid = 0x20655 | | cpuid = 0x20655 | ||
+ | |||
+ | | isa family = x86 | ||
+ | | isa = x86-64 | ||
+ | | microarch = Westmere | ||
+ | | platform = Calpella | ||
+ | | chipset = Ibex Peak | ||
+ | | core name = Arrandale | ||
+ | | core family = 6 | ||
+ | | core model = 37 | ||
+ | | core stepping = K0 | ||
+ | | process = 32 nm | ||
+ | | transistors = 382,000,000 | ||
+ | | technology = CMOS | ||
+ | | die area = 81 mm² | ||
+ | | die width = | ||
+ | | die length = | ||
+ | | word size = 64 bit | ||
+ | | core count = 2 | ||
+ | | thread count = 2 | ||
+ | | max cpus = 1 | ||
+ | | max memory = 8 GiB | ||
+ | |||
+ | |||
+ | | v core = | ||
+ | | v core tolerance = | ||
+ | | v io = | ||
+ | | v io tolerance = | ||
+ | | sdp = | ||
+ | | tdp = 35 W | ||
+ | | tjunc min = 0 °C | ||
+ | | tjunc max = 90 °C | ||
+ | | tcase min = | ||
+ | | tcase max = | ||
+ | | tstorage min = -25 °C | ||
+ | | tstorage max = 125 °C | ||
+ | | tambient min = | ||
+ | | tambient max = | ||
+ | |||
+ | | package module 1 = {{packages/intel/rpga-988a}} | ||
}} | }} | ||
'''Celeron P4600''' is a {{arch|64}} [[dual-core]] [[x86]] mobile microprocessor introduced by [[Intel]] in [[2010]]. This processor operates at a frequency of 2.00 GHz and a TDP of 35 W. This MPU is manufactured on a [[32 nm process]] based on the {{intel|Westmere|l=arch}} microarchitecture ({{intel|Arrandale|l=core}} core). This processor incorporated the {{intel|HD Graphics (Ironlake)}} [[IGP]] on the same package operating at a base frequency of 500.00 MHz and a burst frequency of 667.00 MHz. | '''Celeron P4600''' is a {{arch|64}} [[dual-core]] [[x86]] mobile microprocessor introduced by [[Intel]] in [[2010]]. This processor operates at a frequency of 2.00 GHz and a TDP of 35 W. This MPU is manufactured on a [[32 nm process]] based on the {{intel|Westmere|l=arch}} microarchitecture ({{intel|Arrandale|l=core}} core). This processor incorporated the {{intel|HD Graphics (Ironlake)}} [[IGP]] on the same package operating at a base frequency of 500.00 MHz and a burst frequency of 667.00 MHz. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|intel/microarchitectures/westmere#Memory_Hierarchy|l1=Westmere § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=128 KiB | ||
+ | |l1i cache=64 KiB | ||
+ | |l1i break=2x32 KiB | ||
+ | |l1i desc=4-way set associative | ||
+ | |l1i policy=write-back | ||
+ | |l1d cache=64 KiB | ||
+ | |l1d break=2x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=512 KiB | ||
+ | |l2 break=2x256 KiB | ||
+ | |l2 desc=8-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=2 MiB | ||
+ | |l3 break=2x1 MiB | ||
+ | |l3 desc=8-way set associative | ||
+ | |l3 policy=write-back | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR3-1066 | ||
+ | |ecc=No | ||
+ | |max mem=8 GiB | ||
+ | |controllers=1 | ||
+ | |channels=2 | ||
+ | |max bandwidth=15.88 GiB/s | ||
+ | |bandwidth schan=7.942 GiB/s | ||
+ | |bandwidth dchan=15.88 GiB/s | ||
+ | |pae=36 bit | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | | pcie revision = 2.0 | ||
+ | | pcie lanes = 16 | ||
+ | | pcie config = 1x16 | ||
+ | }} | ||
+ | |||
+ | == Graphics == | ||
+ | {{integrated graphics | ||
+ | | gpu = HD Graphics (Ironlake) | ||
+ | | device id = 0x0046 | ||
+ | | designer = Intel | ||
+ | | execution units = 12 | ||
+ | | max displays = 2 | ||
+ | | max memory = | ||
+ | | frequency = 500 MHz | ||
+ | | max frequency = 667 MHz | ||
+ | |||
+ | | directx ver = 10.1 | ||
+ | | opengl ver = 2.1 | ||
+ | |||
+ | | features = Yes | ||
+ | | intel quick sync = | ||
+ | | intel intru 3d = | ||
+ | | intel insider = | ||
+ | | intel widi = | ||
+ | | intel fdi = Yes | ||
+ | | intel clear video = Yes | ||
+ | | intel clear video hd = | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=No | ||
+ | |sse42=No | ||
+ | |sse4a=No | ||
+ | |avx=No | ||
+ | |avx2=No | ||
+ | |||
+ | |abm=No | ||
+ | |tbm=No | ||
+ | |bmi1=No | ||
+ | |bmi2=No | ||
+ | |fma3=No | ||
+ | |fma4=No | ||
+ | |aes=No | ||
+ | |rdrand=No | ||
+ | |sha=No | ||
+ | |xop=No | ||
+ | |adx=No | ||
+ | |clmul=No | ||
+ | |f16c=No | ||
+ | |tbt1=No | ||
+ | |tbt2=No | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |flex=Yes | ||
+ | |fastmem=Yes | ||
+ | |isrt=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=No | ||
+ | |txt=No | ||
+ | |ht=No | ||
+ | |vpro=No | ||
+ | |vtx=No | ||
+ | |vtd=No | ||
+ | |ept=Yes | ||
+ | |mpx=No | ||
+ | |sgx=No | ||
+ | |securekey=No | ||
+ | |osguard=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdv=No | ||
+ | |rvi=No | ||
+ | }} |
Latest revision as of 16:16, 13 December 2017
Edit Values | ||||||||||||
Intel Celeron P4600 | ||||||||||||
General Info | ||||||||||||
Designer | Intel | |||||||||||
Manufacturer | Intel | |||||||||||
Model Number | P4600 | |||||||||||
Part Number | CP80617005307AB | |||||||||||
S-Spec | SLBZY | |||||||||||
Market | Mobile | |||||||||||
Introduction | March 28, 2010 (announced) March 28, 2010 (launched) | |||||||||||
Shop | Amazon | |||||||||||
General Specs | ||||||||||||
Family | Celeron | |||||||||||
Series | P4000 | |||||||||||
Locked | Yes | |||||||||||
Frequency | 1,999.99 MHz | |||||||||||
Bus type | DMI 1.0 | |||||||||||
Bus rate | 1 × 2.5 GT/s | |||||||||||
Clock multiplier | 15 | |||||||||||
CPUID | 0x20655 | |||||||||||
Microarchitecture | ||||||||||||
ISA | x86-64 (x86) | |||||||||||
Microarchitecture | Westmere | |||||||||||
Platform | Calpella | |||||||||||
Chipset | Ibex Peak | |||||||||||
Core Name | Arrandale | |||||||||||
Core Family | 6 | |||||||||||
Core Model | 37 | |||||||||||
Core Stepping | K0 | |||||||||||
Process | 32 nm | |||||||||||
Transistors | 382,000,000 | |||||||||||
Technology | CMOS | |||||||||||
Die | 81 mm² | |||||||||||
Word Size | 64 bit | |||||||||||
Cores | 2 | |||||||||||
Threads | 2 | |||||||||||
Max Memory | 8 GiB | |||||||||||
Multiprocessing | ||||||||||||
Max SMP | 1-Way (Uniprocessor) | |||||||||||
Electrical | ||||||||||||
TDP | 35 W | |||||||||||
Tjunction | 0 °C – 90 °C | |||||||||||
Tstorage | -25 °C – 125 °C | |||||||||||
Packaging | ||||||||||||
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Celeron P4600 is a 64-bit dual-core x86 mobile microprocessor introduced by Intel in 2010. This processor operates at a frequency of 2.00 GHz and a TDP of 35 W. This MPU is manufactured on a 32 nm process based on the Westmere microarchitecture (Arrandale core). This processor incorporated the HD Graphics (Ironlake) IGP on the same package operating at a base frequency of 500.00 MHz and a burst frequency of 667.00 MHz.
Cache[edit]
- Main article: Westmere § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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Graphics[edit]
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Integrated Graphics Information
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Features[edit]
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Facts about "Celeron P4600 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Celeron P4600 - Intel#package + and Celeron P4600 - Intel#io + |
base frequency | 1,999.99 MHz (2 GHz, 1,999,990 kHz) + |
bus links | 1 + |
bus rate | 2,500 MT/s (2.5 GT/s, 2,500,000 kT/s) + |
bus type | DMI 1.0 + |
chipset | Ibex Peak + |
clock multiplier | 15 + |
core count | 2 + |
core family | 6 + |
core model | 37 + |
core name | Arrandale + |
core stepping | K0 + |
cpuid | 0x20655 + |
designer | Intel + |
device id | 0x0046 + |
die area | 81 mm² (0.126 in², 0.81 cm², 81,000,000 µm²) + |
family | Celeron + |
first announced | March 28, 2010 + |
first launched | March 28, 2010 + |
full page name | intel/celeron/p4600 + |
has ecc memory support | false + |
has extended page tables support | true + |
has feature | Enhanced SpeedStep Technology +, Extended Page Tables + and Flex Memory Access + |
has intel enhanced speedstep technology | true + |
has intel flex memory access support | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
instance of | microprocessor + |
integrated gpu | HD Graphics (Ironlake) + |
integrated gpu base frequency | 500 MHz (0.5 GHz, 500,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 12 + |
integrated gpu max frequency | 667 MHz (0.667 GHz, 667,000 KHz) + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ description | 8-way set associative + |
l3$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
ldate | March 28, 2010 + |
manufacturer | Intel + |
market segment | Mobile + |
max cpu count | 1 + |
max junction temperature | 363.15 K (90 °C, 194 °F, 653.67 °R) + |
max memory | 8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB, 0.00781 TiB) + |
max memory bandwidth | 15.88 GiB/s (16,261.12 MiB/s, 17.051 GB/s, 17,051.02 MB/s, 0.0155 TiB/s, 0.0171 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 16 + |
max storage temperature | 398.15 K (125 °C, 257 °F, 716.67 °R) + |
microarchitecture | Westmere + |
min junction temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min storage temperature | 248.15 K (-25 °C, -13 °F, 446.67 °R) + |
model number | P4600 + |
name | Intel Celeron P4600 + |
package | rPGA-988A + |
part number | CP80617005307AB + |
platform | Calpella + |
process | 32 nm (0.032 μm, 3.2e-5 mm) + |
s-spec | SLBZY + |
series | P4000 + |
smp max ways | 1 + |
supported memory type | DDR3-1066 + |
tdp | 35 W (35,000 mW, 0.0469 hp, 0.035 kW) + |
technology | CMOS + |
thread count | 2 + |
transistor count | 382,000,000 + |
word size | 64 bit (8 octets, 16 nibbles) + |