Semiconductor & Computer Engineering
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Difference between revisions of "intel/celeron/887e"
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Revision as of 15:15, 13 December 2017
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| Celeron 887E | |||||||||
| General Info | |||||||||
| Designer | Intel | ||||||||
| Manufacturer | Intel | ||||||||
| Model Number | 887E | ||||||||
| Part Number | AV8062701082200 | ||||||||
| S-Spec | SR0BV | ||||||||
| Market | Embedded | ||||||||
| Introduction | September, 2012 (announced) September, 2012 (launched) | ||||||||
| Shop | Amazon | ||||||||
| General Specs | |||||||||
| Family | Celeron | ||||||||
| Series | 800 | ||||||||
| Locked | Yes | ||||||||
| Frequency | 1,500 MHz | ||||||||
| Bus type | DMI 2.0 | ||||||||
| Bus rate | 4 × 5 GT/s | ||||||||
| Clock multiplier | 15 | ||||||||
| CPUID | 0x206A7 | ||||||||
| Microarchitecture | |||||||||
| ISA | x86-64 (x86) | ||||||||
| Microarchitecture | Sandy Bridge | ||||||||
| Platform | Sandy Bridge M | ||||||||
| Chipset | Cougar Point | ||||||||
| Core Name | Sandy Bridge M | ||||||||
| Core Family | 6 | ||||||||
| Core Model | 42 | ||||||||
| Core Stepping | Q0 | ||||||||
| Process | 32 nm | ||||||||
| Transistors | 504,000,000 | ||||||||
| Technology | CMOS | ||||||||
| Die | 131 mm² | ||||||||
| Word Size | 64 bit | ||||||||
| Cores | 2 | ||||||||
| Threads | 2 | ||||||||
| Max Memory | 16 GiB | ||||||||
| Multiprocessing | |||||||||
| Max SMP | 1-Way (Uniprocessor) | ||||||||
| Electrical | |||||||||
| Power (idle) | 2.3 W | ||||||||
| Vcore | 0.3 V-1.52 V | ||||||||
| TDP | 17 W | ||||||||
| Tjunction | 0 °C – 100 °C | ||||||||
| Tstorage | -25 °C – 125 °C | ||||||||
| Packaging | |||||||||
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Celeron 887E is a dual-core budget mobile embedded x86 microprocessor introduced by Intel in late 2012. The Celeron 887E, which is based on the Sandy Bridge microarchitecture and is manufactured on a 32 nm process, operates at 1.5 GHz with a TDP of 17 W. This chip incorporates Intel's HD Graphics integrated graphics operating at 350 MHz with a bust frequency of 1 GHz. This processor supports 16 GiB of dual-channel DDR3-1333 ECC memory.
Contents
Cache
- Main article: Sandy Bridge § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options |
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Graphics
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Integrated Graphics Information
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| [Edit] Sandy Bridge (Gen6) Hardware Accelerated Video Capabilities | |||||||
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| Codec | Encode | Decode | |||||
| Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
| MPEG-2 (H.262) | ✘ | Main | Main, High | Up to 80 Mbps | |||
| MPEG-4 AVC (H.264) | Main | 4.1 | Up to 40 Mbps | Main, High | 4.1 | Up to 40 Mbps | |
| VC-1 | ✘ | Advanced, Main, Simple | 3, High, Simple | Up to 40 Mbps | |||
Features
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Documents
Datasheet
Other
Facts about "Celeron 887E - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Celeron 887E - Intel#pcie + |
| device id | 0x0106 + |
| has ecc memory support | true + |
| has feature | Enhanced SpeedStep Technology +, Intel VT-x + and Flex Memory Access + |
| has intel enhanced speedstep technology | true + |
| has intel flex memory access support | true + |
| has intel vt-x technology | true + |
| integrated gpu | HD Graphics (Sandy Bridge) + |
| integrated gpu base frequency | 350 MHz (0.35 GHz, 350,000 KHz) + |
| integrated gpu designer | Intel + |
| integrated gpu execution units | 6 + |
| integrated gpu max frequency | 1,000 MHz (1 GHz, 1,000,000 KHz) + |
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
| l3$ description | 8-way set associative + |
| l3$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
| max memory bandwidth | 19.87 GiB/s (20,346.88 MiB/s, 21.335 GB/s, 21,335.25 MB/s, 0.0194 TiB/s, 0.0213 TB/s) + |
| max memory channels | 2 + |
| supported memory type | DDR3-1333 + and DDR3-1066 + |