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{{intel title|Atom Z620}}
 
{{intel title|Atom Z620}}
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{{mpu
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{{chip
 
| name                = Atom Z620
 
| name                = Atom Z620
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| no image            = Yes
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| image              = lincroft chips.png
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| image              =  
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| image size          = 250px
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| image size          =  
 
 
| caption            =  
 
| caption            =  
 
| designer            = Intel
 
| designer            = Intel
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| model number        = Z620
 
| model number        = Z620
 
| part number        = AY80609003996AC
 
| part number        = AY80609003996AC
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| part number 1      =
 
 
| part number 2      =  
 
| part number 2      =  
 
| part number 3      =  
 
| part number 3      =  
 +
| part number 4      =
 
| s-spec              = SLBZE
 
| s-spec              = SLBZE
 
| s-spec 2            =  
 
| s-spec 2            =  
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| max memory          = 2 GiB
 
| max memory          = 2 GiB
  
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| electrical          = Yes
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| power              =  
 
| power              =  
 
| average power      =  
 
| average power      =  
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'''Atom Z620''' is an ultra-low power {{arch|32}} [[x86]] system on a chip designed by [[Intel]] and introduced in early [[2010]]. The Z620, which is based on the {{intel|Bonnell|l=arch}} microarchitecture ({{intel|Lincroft|l=core}} core), is fabricated on a [[45 nm process]]. This SoC incorporates a single core operating at 900 MHz with a low frequency mode of 600 MHz and a burst frequency of 1.5 GHz. The chip has a TDP of 1.3 W and supporting up to a 2 GiB of single-channel DDR2-800 memory. Additionally, the Z620 incorporates a {{imgtec|PowerVR SGX 535|GMA 600}} [[IGP]] operating at 400 MHz.
 
'''Atom Z620''' is an ultra-low power {{arch|32}} [[x86]] system on a chip designed by [[Intel]] and introduced in early [[2010]]. The Z620, which is based on the {{intel|Bonnell|l=arch}} microarchitecture ({{intel|Lincroft|l=core}} core), is fabricated on a [[45 nm process]]. This SoC incorporates a single core operating at 900 MHz with a low frequency mode of 600 MHz and a burst frequency of 1.5 GHz. The chip has a TDP of 1.3 W and supporting up to a 2 GiB of single-channel DDR2-800 memory. Additionally, the Z620 incorporates a {{imgtec|PowerVR SGX 535|GMA 600}} [[IGP]] operating at 400 MHz.
  
 +
This chip communicates with the [[southbridge]] chipset (PCH MP30) over two buses: cDMI and cDVO. Both buses go from the SoC to the chipset. cDMI, which is used as the data interface link, operates at 100 MHz using a quad-pumped rate (i.e. 400 MT/s). That bus is composed of an 8-bit transmit and 8-bit receive. The cDVO, which is used as a unidirectional display data link is a quad-pumped 6-bit bus operating 100 MHz for a 400 MT/s effective rate. This model uses CMOS signaling for both buses.
 
== Cache ==
 
== Cache ==
 
{{main|intel/microarchitectures/bonnell#Memory_Hierarchy|l1=Bonnell § Cache}}
 
{{main|intel/microarchitectures/bonnell#Memory_Hierarchy|l1=Bonnell § Cache}}
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| max displays        = 1
 
| max displays        = 1
 
| max memory          = 256 MiB
 
| max memory          = 256 MiB
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| frequency          = 200 MHz
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| frequency          = 400 MHz
  
 
| output dsi          = Yes
 
| output dsi          = Yes
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|avx=No
 
|avx=No
 
|avx2=No
 
|avx2=No
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|avx512=No
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|abm=No
 
|abm=No
 
|tbm=No
 
|tbm=No
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|xfr=No
 
|xfr=No
 
}}
 
}}
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== Die Shot ==
 +
{{see also|intel/microarchitectures/bonnell#Lincroft|l1=Bonnell § Lincroft Die}}
 +
* [[45 nm process]]
 +
* 140,000,000
 +
* Die size 7.34 mm × 8.89 mm
 +
* Size area 65.2526 mm²
 +
[[File:lincroft die shot.png|500px]]
 +
 +
[[File:lincroft die shot (annotated).png|500px]]
 +
 +
 +
[[File:lincroft die shot 2.png|500px]]
 +
 +
[[File:lincroft die shot 2 (annotated).png|500px]]
 +
 +
== Documents ==
 +
=== Datasheet ===
 +
* [[:File:atom-z6xx-datasheet.pdf|Atom Z6xx Datasheet]], May 2011
 +
* [[:File:atom-z6xx-specification-update.pdf|Atom Z6xx Specs Update]], May 2011

Latest revision as of 15:14, 13 December 2017

Edit Values
Atom Z620
lincroft chips.png
General Info
DesignerIntel
ManufacturerIntel
Model NumberZ620
Part NumberAY80609003996AC
S-SpecSLBZE
MarketMobile
IntroductionMay 4, 2010 (announced)
May 4, 2010 (launched)
ShopAmazon
General Specs
FamilyAtom
SeriesZ620
LockedYes
Frequency900 MHz
Turbo FrequencyYes
Turbo Frequency1,600 MHz (1 core)
Bus typecDMI
Bus speed100 MHz
Bus rate400 MT/s
Clock multiplier9
CPUID20661
Microarchitecture
ISAx86-32 (x86)
MicroarchitectureBonnell
PlatformMoorestown
ChipsetLangwell
Core NameLincroft
Core Family6
Core Model38
Core Stepping1
Process45 nm
Transistors140,000,000
TechnologyCMOS
Die65.2526 mm²
8.89 mm × 7.34 mm
Word Size32 bit
Cores1
Threads2
Max Memory2 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore0.75 V-1.2 V
TDP1.3 W
Tjunction-25 °C – 90 °C
Tstorage-55 °C – 125 °C
Packaging
PackageFCBGA-518 (FCBGA)
Dimension13.8 mm x 13.8 mm x 1.1 mm
Pin Count518
SocketBGA-518 (BGA)

Atom Z620 is an ultra-low power 32-bit x86 system on a chip designed by Intel and introduced in early 2010. The Z620, which is based on the Bonnell microarchitecture (Lincroft core), is fabricated on a 45 nm process. This SoC incorporates a single core operating at 900 MHz with a low frequency mode of 600 MHz and a burst frequency of 1.5 GHz. The chip has a TDP of 1.3 W and supporting up to a 2 GiB of single-channel DDR2-800 memory. Additionally, the Z620 incorporates a GMA 600 IGP operating at 400 MHz.

This chip communicates with the southbridge chipset (PCH MP30) over two buses: cDMI and cDVO. Both buses go from the SoC to the chipset. cDMI, which is used as the data interface link, operates at 100 MHz using a quad-pumped rate (i.e. 400 MT/s). That bus is composed of an 8-bit transmit and 8-bit receive. The cDVO, which is used as a unidirectional display data link is a quad-pumped 6-bit bus operating 100 MHz for a 400 MT/s effective rate. This model uses CMOS signaling for both buses.

Cache[edit]

Main article: Bonnell § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$56 KiB
57,344 B
0.0547 MiB
L1I$32 KiB
32,768 B
0.0313 MiB
1x32 KiB8-way set associative 
L1D$24 KiB
24,576 B
0.0234 MiB
1x24 KiB6-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  1x512 KiB8-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR-400, DDR2-800
Supports ECCNo
Max Mem2 GiB
Controllers1
Channels1
Width32 bit
Max Bandwidth2.98 GiB/s
3,051.52 MiB/s
3.2 GB/s
3,199.751 MB/s
0.00291 TiB/s
0.0032 TB/s
Bandwidth
Single 2.98 GiB/s
Physical Address (PAE)32 bit

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
USB
Revision2.0
Ports4
UART
GP I/OYes


Graphics[edit]

This chip incroporates the "GMA 600" integrated graphics which is actually a re-branded licensed Imagination PowerVR SGX 535 IGP.

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR SGX535
DesignerImagination Technologies
Max Displays1
Max Memory256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
Frequency400 MHz
0.4 GHz
400,000 KHz
OutputDSI, LVDS
Max Resolution
DSI1024x600
LVDS1366x768
Standards
Direct3D9.0c
OpenGL2.1
OpenGL ES1.1, 2.0
OpenVG1.1
Additional Features
Intel Clear Video
  • Supports hardware-accelerated HD video decode (MPEG4 part 2, H.264, WMV, and VC1)
  • Supports hardware-accelerated HD video encode (MPEG4 part 2 and H.264)

Features[edit]

Die Shot[edit]

See also: Bonnell § Lincroft Die
  • 45 nm process
  • 140,000,000
  • Die size 7.34 mm × 8.89 mm
  • Size area 65.2526 mm²

lincroft die shot.png

lincroft die shot (annotated).png


lincroft die shot 2.png

lincroft die shot 2 (annotated).png

Documents[edit]

Datasheet[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/atom/z620&oldid=70413"
Facts about "Atom Z620 - Intel"
RDF feed
has ecc memory supportfalse +
has featureHyper-Threading Technology +, Burst Performance Technology + and Enhanced SpeedStep Technology +
has intel burst performance technologytrue +
has intel enhanced speedstep technologytrue +
has simultaneous multithreadingtrue +
integrated gpuPowerVR SGX535 +
integrated gpu base frequency200 MHz (0.2 GHz, 200,000 KHz) +
integrated gpu designerImagination Technologies +
integrated gpu max memory256 MiB (262,144 KiB, 268,435,456 B, 0.25 GiB) +
l1$ size56 KiB (57,344 B, 0.0547 MiB) +
l1d$ description6-way set associative +
l1d$ size24 KiB (24,576 B, 0.0234 MiB) +
l1i$ description8-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
l2$ description8-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
max memory bandwidth2.98 GiB/s (3,051.52 MiB/s, 3.2 GB/s, 3,199.751 MB/s, 0.00291 TiB/s, 0.0032 TB/s) +
max memory channels1 +
supported memory typeDDR-400 + and DDR2-800 +