Semiconductor & Computer Engineering
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Difference between revisions of "intel/80486/486dx4-75"
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{{intel title|i486DX4-75}} | {{intel title|i486DX4-75}} | ||
| − | {{ | + | {{chip |
| name = Intel i486DX4-75 | | name = Intel i486DX4-75 | ||
| image = Ic-photo-Intel--FC80486DX4-75--(486-CPU).png | | image = Ic-photo-Intel--FC80486DX4-75--(486-CPU).png | ||
| Line 55: | Line 55: | ||
| core count = 1 | | core count = 1 | ||
| max cpus = 1 | | max cpus = 1 | ||
| − | | max memory = 4 | + | | max memory = 4 GiB |
| + | |||
| − | |||
| power = 2.72 W | | power = 2.72 W | ||
| v core = 3.3 V | | v core = 3.3 V | ||
| Line 79: | Line 79: | ||
== Cache == | == Cache == | ||
{{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | {{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | ||
| + | The i486dx4-100 was offered with two cache policies. Models that came with a write-back cache were marked by an "'''&EW'''" identifier. Models that came with a write-through policy were marked by "'''&E'''". | ||
{{cache info | {{cache info | ||
| − | |l1 cache=16 | + | |l1 cache=16 KiB |
| − | |l1 break=1x16 | + | |l1 break=1x16 KiB |
|l1 desc=4-way set associative | |l1 desc=4-way set associative | ||
| − | |l1 extra=(unified, write-through policy) | + | |l1 extra=(unified, write-through/write-back policy) |
}} | }} | ||
| Line 91: | Line 92: | ||
== Features == | == Features == | ||
* {{intel|System Management Mode}} (SMM) | * {{intel|System Management Mode}} (SMM) | ||
| + | |||
| + | == Gallery == | ||
| + | <gallery> | ||
| + | File:KL Intel i486DX4-75 PQFP.jpg|FC80486DX4-75, S-Spec SX883 | ||
| + | </gallery> | ||
== See also == | == See also == | ||
* {{intel|80486|80486 family}} | * {{intel|80486|80486 family}} | ||
Latest revision as of 15:13, 13 December 2017
| Edit Values | |
| Intel i486DX4-75 | |
 | |
| FC80486DX4, S-Spec SK052 | |
| General Info | |
| Designer | Intel |
| Manufacturer | Intel |
| Model Number | i486DX4-75 |
| Part Number | A80486DX4-75, MA80486DX4-75, MQ80486DX4-75, TQ80486DX475, FC80486DX4-75, FC80486DX4WB75 |
| S-Spec | SK047, SK087, SK102, SX871, SX884, SK052, SK100, SX870, SX883 |
| Introduction | March 7, 1994 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | 80486 |
| Series | 486DX4 |
| Frequency | 75 MHz |
| Bus type | FSB |
| Bus speed | 25 MHz |
| Bus rate | 25 MT/s |
| Clock multiplier | 3 |
| CPUID | 480 |
| Microarchitecture | |
| Microarchitecture | 80486 |
| Core Name | 486DX4 |
| Process | 600 nm |
| Transistors | 1,600,000 |
| Technology | CMOS |
| Word Size | 32 bit |
| Cores | 1 |
| Max Memory | 4 GiB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Power dissipation | 2.72 W |
| Vcore | 3.3 V ± 0.3 V |
| OP Temperature | 0 °C – 85 °C |
i486DX4-75 was a fourth-generation x86 microprocessor introduced by Intel in 1994. This chip, which is based on the 80486 microarchitecture, had a clock multiplier of x2, x2.5, and x3 with a max operating frequency of 75 MHz, three times the bus frequency. Like the original i486DX, this chip implemented the 80387 FPU on-die and incorporated System Management Mode (SMM). The DX4 series had twice as much cache space as the older processors.
Contents
Cache[edit]
- Main article: 80486 § Cache
The i486dx4-100 was offered with two cache policies. Models that came with a write-back cache were marked by an "&EW" identifier. Models that came with a write-through policy were marked by "&E".
| Cache Info [Edit Values] | ||
| L1$ | 16 KiB 16,384 B 0.0156 MiB |
1x16 KiB 4-way set associative (unified, write-through/write-back policy) |
Graphics[edit]
This chip had no integrated graphics processing unit.
Features[edit]
- System Management Mode (SMM)
Gallery[edit]
FC80486DX4-75, S-Spec SX883
