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Difference between revisions of "intel/80486/486dx4-100"
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{{intel title|i486DX4-100}}
 
{{intel title|i486DX4-100}}
−
{{mpu
+
{{chip
 
| name                = Intel i486DX4-100
 
| name                = Intel i486DX4-100
 
| image              = I486DX4.jpg
 
| image              = I486DX4.jpg
Line 44: Line 44:
 
| s-spec 13          = SX906
 
| s-spec 13          = SX906
 
| s-spec es          =  
 
| s-spec es          =  
−
| s-spec qs           = Q0746
+
| s-spec qs 2        = Q0746
−
| s-spec qs           = Q0747
+
| s-spec qs 3        = Q0747
−
| s-spec qs           = Q860
+
| s-spec qs 4        = Q860
 
| cpuid              = 480
 
| cpuid              = 480
−
| cpuid               = 483
+
| cpuid 2            = 483
  
 
| microarch          = 80486
 
| microarch          = 80486
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| core count          = 1
 
| core count          = 1
 
| max cpus            = 1
 
| max cpus            = 1
−
| max memory          = 4 GB
+
| max memory          = 4 GiB
 +
 
  
−
| electrical          = Yes
 
 
| power              = 3.55 W
 
| power              = 3.55 W
 
| v core              = 3.3 V
 
| v core              = 3.3 V
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== Cache ==
 
== Cache ==
 
{{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}}
 
{{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}}
 +
The i486dx4-100 was offered with two cache policies. Models that came with a write-back cache were marked by an "'''&EW'''" identifier. Models that came with a write-through policy were marked by "'''&E'''".
 
{{cache info
 
{{cache info
−
|l1 cache=16 KB
+
|l1 cache=16 KiB
−
|l1 break=1x16 KB
+
|l1 break=1x16 KiB
 
|l1 desc=4-way set associative
 
|l1 desc=4-way set associative
−
|l1 extra=(unified, write-through policy)
+
|l1 extra=(unified, write-through/write-back policy)
 
}}
 
}}
  
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Ic-photo-intel-A80486DX4100-(486DX4).png|A80486DX4100, S-Spec SK096
 
Ic-photo-intel-A80486DX4100-(486DX4).png|A80486DX4100, S-Spec SK096
 
File:Intel DX4 microprocessor.jpg|A80486DX4100, S-Spec SK096
 
File:Intel DX4 microprocessor.jpg|A80486DX4100, S-Spec SK096
 +
File:Intel i486 DX4 100 MHz SK051.jpeg|A80486DX4100, S-Spec SK051
 +
File:Intel i486 DX4 100 SK051.jpg|A80486DX4100, S-Spec SK051
 
</gallery>
 
</gallery>
  
 
== See also ==
 
== See also ==
 
* {{intel|80486|80486 family}}
 
* {{intel|80486|80486 family}}

Latest revision as of 15:13, 13 December 2017

Edit Values
Intel i486DX4-100
I486DX4.jpg
A80486DX4-100, S-Spec SX900
General Info
DesignerIntel
ManufacturerIntel
Model Numberi486DX4-100
Part NumberA80486DX4-100,
A80486DX4WB100,
MA80486DX4-100,
TQ80486DX4100,
MQ80486DX4-100,
MQ80486DX4100,
FC80486DX4-100,
FC80486DX4WB100
S-SpecSK050, SK051, SK096, SK851, SX877, SX900, SX908, SK053, SK063, SK099, SL2M9, SX876, SX906
IntroductionMarch 7, 1994 (launched)
ShopAmazon
General Specs
Family80486
Series486DX4
Frequency100 MHz
Bus typeFSB
Bus speed33 MHz
Bus rate33 MT/s
Clock multiplier3
CPUID480, 483
Microarchitecture
Microarchitecture80486
Core Name486DX4
Process600 nm
Transistors1,600,000
TechnologyCMOS
Word Size32 bit
Cores1
Max Memory4 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Power dissipation3.55 W
Vcore3.3 V ± 0.3 V
OP Temperature0 °C – 85 °C

i486DX4-100 was a fourth-generation x86 microprocessor introduced by Intel in 1994. This chip, which is based on the 80486 microarchitecture, had a clock multiplier of x2, x2.5, and x3 with a max operating frequency of 100 MHz, three times the bus frequency. Like the original i486DX, this chip implemented the 80387 FPU on-die and incorporated System Management Mode (SMM). The DX4 series had twice as much cache space as the older processors.

Cache[edit]

Main article: 80486 § Cache

The i486dx4-100 was offered with two cache policies. Models that came with a write-back cache were marked by an "&EW" identifier. Models that came with a write-through policy were marked by "&E".

Cache Info [Edit Values]
L1$ 16 KiB
16,384 B
0.0156 MiB
1x16 KiB 4-way set associative (unified, write-through/write-back policy)

Graphics[edit]

This chip had no integrated graphics processing unit.

Features[edit]

Gallery[edit]

  • A80486DX4100, S-Spec SK096

  • A80486DX4100, S-Spec SK096

  • A80486DX4100, S-Spec SK096

  • A80486DX4100, S-Spec SK051

  • A80486DX4100, S-Spec SK051

See also[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/80486/486dx4-100&oldid=70365"
Facts about "i486DX4-100 - Intel"
RDF feed
base frequency100 MHz (0.1 GHz, 100,000 kHz) +
bus rate33 MT/s (0.033 GT/s, 33,000 kT/s) +
bus speed33 MHz (0.033 GHz, 33,000 kHz) +
bus typeFSB +
clock multiplier3 +
core count1 +
core name486DX4 +
core voltage3.3 V (33 dV, 330 cV, 3,300 mV) +
core voltage tolerance0.3 V +
cpuid480 + and 483 +
designerIntel +
family80486 +
first launchedMarch 7, 1994 +
full page nameintel/80486/486dx4-100 +
instance ofmicroprocessor +
l1$ description4-way set associative +
l1$ size16 KiB (16,384 B, 0.0156 MiB) +
ldateMarch 7, 1994 +
main imageFile:I486DX4.jpg +
main image captionA80486DX4-100, S-Spec SX900 +
manufacturerIntel +
max cpu count1 +
max memory4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
max operating temperature85 °C +
microarchitecture80486 +
min operating temperature0 °C +
model numberi486DX4-100 +
nameIntel i486DX4-100 +
part numberA80486DX4-100 +, A80486DX4WB100 +, MA80486DX4-100 +, TQ80486DX4100 +, MQ80486DX4-100 +, MQ80486DX4100 +, FC80486DX4-100 + and FC80486DX4WB100 +
power dissipation3.55 W (3,550 mW, 0.00476 hp, 0.00355 kW) +
process600 nm (0.6 μm, 6.0e-4 mm) +
s-specSK050 +, SK051 +, SK096 +, SK851 +, SX877 +, SX900 +, SX908 +, SK053 +, SK063 +, SK099 +, SL2M9 +, SX876 + and SX906 +
series486DX4 +
smp max ways1 +
technologyCMOS +
transistor count1,600,000 +
word size32 bit (4 octets, 8 nibbles) +