Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/80486/486dx2-50"
m (Bot: moving all {{mpu}} to {{chip}}) |
|||
| (7 intermediate revisions by 3 users not shown) | |||
| Line 1: | Line 1: | ||
{{intel title|i486DX2-50}} | {{intel title|i486DX2-50}} | ||
| − | {{ | + | {{chip |
| name = Intel i486DX2-50 | | name = Intel i486DX2-50 | ||
| image = Ic-photo-Intel--SB80486DX2-50--(486-CPU).JPG | | image = Ic-photo-Intel--SB80486DX2-50--(486-CPU).JPG | ||
| Line 37: | Line 37: | ||
| s-spec 9 = SX768 | | s-spec 9 = SX768 | ||
| s-spec 10 = SX808 | | s-spec 10 = SX808 | ||
| − | | s-spec 11 = SX912 | + | | s-spec 11 = SX825 |
| − | | s-spec | + | | s-spec 12 = SX912 |
| + | | s-spec 13 = SX920 | ||
| + | | s-spec 14 = SX954 | ||
| s-spec es = | | s-spec es = | ||
| s-spec qs = Q0382 | | s-spec qs = Q0382 | ||
| Line 62: | Line 64: | ||
| core count = 1 | | core count = 1 | ||
| max cpus = 1 | | max cpus = 1 | ||
| − | | max memory = 4 | + | | max memory = 4 GiB |
| + | |||
| − | |||
| power = 3.88 W | | power = 3.88 W | ||
| v core = 5 V | | v core = 5 V | ||
| Line 88: | Line 90: | ||
{{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | {{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | ||
{{cache info | {{cache info | ||
| − | |l1 cache=8 | + | |l1 cache=8 KiB |
| − | |l1 break=1x8 | + | |l1 break=1x8 KiB |
|l1 desc=4-way set associative | |l1 desc=4-way set associative | ||
| − | |l1 extra=(unified, write-through policy ) | + | |l1 extra=(unified, write-through policy) |
}} | }} | ||
| Line 103: | Line 105: | ||
<gallery> | <gallery> | ||
File:Ic-photo-intel-A80486DX2-50-(486DX2).png|A80486DX2-50, S-Spec SX808 | File:Ic-photo-intel-A80486DX2-50-(486DX2).png|A80486DX2-50, S-Spec SX808 | ||
| + | File:Intel i486 DX2-50 MHz.jpg|A80486DX2-50, S-Spec SX641 | ||
| + | File:KL Intel i486DX2 PQFP.jpg|SB80486DX2-50, S-Spec SX920 | ||
| + | File:Sb80486dx2-50 sx825 observe.png|SB80486DX2-50, S-Spec SX825 | ||
</gallery> | </gallery> | ||
== See also == | == See also == | ||
* {{intel|80486|80486 family}} | * {{intel|80486|80486 family}} | ||
Latest revision as of 15:13, 13 December 2017
| Edit Values | |
| Intel i486DX2-50 | |
 | |
| SB80486DX2-50 | |
| General Info | |
| Designer | Intel |
| Manufacturer | Intel |
| Model Number | i486DX2-50 |
| Part Number | A80486DX2-50, MA80486DX2-50, MQ80486DX2-50, TQ80486DX250, SB80486DX2-50 |
| S-Spec | SX626, SX627, SX641, SX721, SX738, SX749, SX760, SX761, SX768, SX808, SX825, SX912, SX920, SX954 Q0382 (QS), Q0424 (QS) |
| Introduction | March 3, 1992 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | 80486 |
| Series | 486DX2 |
| Frequency | 50 MHz |
| Bus type | FSB |
| Bus speed | 25 MHz |
| Bus rate | 25 MT/s |
| Clock multiplier | 2 |
| CPUID | 432, 433, 435, 436 |
| Microarchitecture | |
| Microarchitecture | 80486 |
| Core Name | 486DX2 |
| Process | 1 µm, 800 nm |
| Technology | CMOS |
| Word Size | 32 bit |
| Cores | 1 |
| Max Memory | 4 GiB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Power dissipation | 3.88 W |
| Vcore | 5 V ± 5% |
| OP Temperature | 0 °C – 85 °C |
i486DX2-50 was a fourth-generation x86 microprocessor introduced by Intel in 1992. This chip, which is based on the 80486 microarchitecture, had a clock doubler operating at 50 MHz, twice the bus frequency. Like the original i486DX, this chip implemented the 80387 FPU on-die and incorporated System Management Mode (SMM).
Contents
Cache[edit]
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 8 KiB 8,192 B 0.00781 MiB |
1x8 KiB 4-way set associative (unified, write-through policy) |
Graphics[edit]
This chip had no integrated graphics processing unit.
Features[edit]
- System Management Mode (SMM)
Gallery[edit]
A80486DX2-50, S-Spec SX808
A80486DX2-50, S-Spec SX641
SB80486DX2-50, S-Spec SX920
SB80486DX2-50, S-Spec SX825
.png)
See also[edit]
Facts about "i486DX2-50 - Intel"
| base frequency | 50 MHz (0.05 GHz, 50,000 kHz) + |
| bus rate | 25 MT/s (0.025 GT/s, 25,000 kT/s) + |
| bus speed | 25 MHz (0.025 GHz, 25,000 kHz) + |
| bus type | FSB + |
| clock multiplier | 2 + |
| core count | 1 + |
| core name | 486DX2 + |
| core voltage | 5 V (50 dV, 500 cV, 5,000 mV) + |
| core voltage tolerance | 5% + |
| cpuid | 432 +, 433 +, 435 + and 436 + |
| designer | Intel + |
| family | 80486 + |
| first launched | March 3, 1992 + |
| full page name | intel/80486/486dx2-50 + |
| instance of | microprocessor + |
| l1$ description | 4-way set associative + |
| l1$ size | 8 KiB (8,192 B, 0.00781 MiB) + |
| ldate | March 3, 1992 + |
| main image | .JPG) + |
| main image caption | SB80486DX2-50 + |
| manufacturer | Intel + |
| max cpu count | 1 + |
| max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
| max operating temperature | 85 °C + |
| microarchitecture | 80486 + |
| min operating temperature | 0 °C + |
| model number | i486DX2-50 + |
| name | Intel i486DX2-50 + |
| part number | A80486DX2-50 +, MA80486DX2-50 +, MQ80486DX2-50 +, TQ80486DX250 + and SB80486DX2-50 + |
| power dissipation | 3.88 W (3,880 mW, 0.0052 hp, 0.00388 kW) + |
| process | 1,000 nm (1 μm, 0.001 mm) + and 800 nm (0.8 μm, 8.0e-4 mm) + |
| s-spec | SX626 +, SX627 +, SX641 +, SX721 +, SX738 +, SX749 +, SX760 +, SX761 +, SX768 +, SX808 +, SX825 +, SX912 +, SX920 + and SX954 + |
| s-spec (qs) | Q0382 + and Q0424 + |
| series | 486DX2 + |
| smp max ways | 1 + |
| technology | CMOS + |
| word size | 32 bit (4 octets, 8 nibbles) + |
.JPG){kind=link}