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Difference between revisions of "freescale/qoriq/p1013"
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{{freescale title|QorIQ P1013}} | {{freescale title|QorIQ P1013}} | ||
− | {{ | + | {{chip |
|name=QorIQ P1013 | |name=QorIQ P1013 | ||
|image=qoriq freescale pbgaii.png | |image=qoriq freescale pbgaii.png | ||
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|market=Networking | |market=Networking | ||
|market 2=Embedded | |market 2=Embedded | ||
+ | |first announced=September 9, 2009 | ||
+ | |first launched=2010 | ||
|family=QorIQ | |family=QorIQ | ||
|series=P1 | |series=P1 | ||
+ | |frequency=1,067 MHz | ||
|isa=Power ISA v2.03 | |isa=Power ISA v2.03 | ||
|isa family=Power | |isa family=Power | ||
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|package module 1={{packages/freescale/te-pbga-ii-689}} | |package module 1={{packages/freescale/te-pbga-ii-689}} | ||
}} | }} | ||
+ | '''QorIQ P1013''' is a {{arch|32}} embedded [[POWER]] microprocessor introduced by [[Freescale]] in late [[2009]]. This networking/embedded processor, which is based on the {{freescale|e500|l=arch}} microarchitecture and is fabricated on a [[45 nm SOI process]], operates at 1,067 MHz and supports 64-bit DDR3-800 memory. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|freescale/microarchitectures/e500#Memory_Hierarchy|l1=e500 § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=64 KiB | ||
+ | |l1i cache=32 KiB | ||
+ | |l1i break=1x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=32 KiB | ||
+ | |l1d break=1x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy= | ||
+ | |l2 cache=256 KiB | ||
+ | |l2 break=1x256 KiB | ||
+ | |l2 desc=8-way set associative | ||
+ | |l2 policy=Write-through | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR3-800 | ||
+ | |ecc=Yes | ||
+ | |controllers=1 | ||
+ | |channels=1 | ||
+ | |width=64 bit | ||
+ | |max bandwidth=5.96 GiB/s | ||
+ | |bandwidth schan=5.96 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | * 3x 10/100/1000 Ethernet with 2x SGMII | ||
+ | * x4+1 PCIe 1.0 interface | ||
+ | * 2x USB 2.0 | ||
+ | * SD/MMC | ||
+ | * SPI | ||
+ | * 2x I2C | ||
+ | * UART | ||
+ | |||
+ | == Block Diagram == | ||
+ | : [[File:qoriq p1013 block diagram.png|800px]] | ||
+ | |||
+ | == Documents == | ||
+ | * [[:File:p1013-p1022.pdf|P1013/P1022 Product Brief]] |
Latest revision as of 16:13, 13 December 2017
Edit Values | |||||||
QorIQ P1013 | |||||||
![]() | |||||||
General Info | |||||||
Designer | Freescale | ||||||
Manufacturer | IBM | ||||||
Model Number | P1013 | ||||||
Market | Networking, Embedded | ||||||
Introduction | September 9, 2009 (announced) 2010 (launched) | ||||||
General Specs | |||||||
Family | QorIQ | ||||||
Series | P1 | ||||||
Frequency | 1,067 MHz | ||||||
Microarchitecture | |||||||
ISA | Power ISA v2.03 (Power) | ||||||
Microarchitecture | e500 | ||||||
Core Name | e500 v2 | ||||||
Process | 45 nm | ||||||
Technology | CMOS | ||||||
Word Size | 32 bit | ||||||
Cores | 1 | ||||||
Threads | 1 | ||||||
Electrical | |||||||
Power dissipation | 3 W | ||||||
Packaging | |||||||
|
QorIQ P1013 is a 32-bit embedded POWER microprocessor introduced by Freescale in late 2009. This networking/embedded processor, which is based on the e500 microarchitecture and is fabricated on a 45 nm SOI process, operates at 1,067 MHz and supports 64-bit DDR3-800 memory.
Cache[edit]
- Main article: e500 § Cache
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
![]() |
Integrated Memory Controller
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Expansions[edit]
- 3x 10/100/1000 Ethernet with 2x SGMII
- x4+1 PCIe 1.0 interface
- 2x USB 2.0
- SD/MMC
- SPI
- 2x I2C
- UART
Block Diagram[edit]
Documents[edit]
Facts about "QorIQ P1013 - Freescale"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | QorIQ P1013 - Freescale#package + |
base frequency | 1,067 MHz (1.067 GHz, 1,067,000 kHz) + |
core count | 1 + |
core name | e500 v2 + |
designer | Freescale + |
family | QorIQ + |
first announced | September 9, 2009 + |
first launched | 2010 + |
full page name | freescale/qoriq/p1013 + |
has ecc memory support | true + |
instance of | microprocessor + |
isa | Power ISA v2.03 + |
isa family | Power + |
l1$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |
ldate | 2010 + |
main image | ![]() |
manufacturer | IBM + |
market segment | Networking + and Embedded + |
max memory bandwidth | 5.96 GiB/s (6,103.04 MiB/s, 6.4 GB/s, 6,399.501 MB/s, 0.00582 TiB/s, 0.0064 TB/s) + |
max memory channels | 1 + |
microarchitecture | e500 + |
model number | P1013 + |
name | QorIQ P1013 + |
package | TE-PBGA-II-689 + |
power dissipation | 3 W (3,000 mW, 0.00402 hp, 0.003 kW) + |
process | 45 nm (0.045 μm, 4.5e-5 mm) + |
series | P1 + |
supported memory type | DDR3-800 + |
technology | CMOS + |
thread count | 1 + |
word size | 32 bit (4 octets, 8 nibbles) + |