Semiconductor & Computer Engineering
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Difference between revisions of "exponential technology/x704/410"
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{{expotech title|X704-410}} | {{expotech title|X704-410}} | ||
| − | {{ | + | {{chip |
| name = X704-410 | | name = X704-410 | ||
| no image = Yes | | no image = Yes | ||
| Line 11: | Line 11: | ||
| part number = | | part number = | ||
| market = Desktop | | market = Desktop | ||
| − | | first announced = | + | | first announced = |
| first launched = March, 1997 | | first launched = March, 1997 | ||
| last order = March, 1997 | | last order = March, 1997 | ||
| Line 43: | Line 43: | ||
| max memory addr = | | max memory addr = | ||
| − | + | ||
| power = 85 W | | power = 85 W | ||
| v core = 3.6 V | | v core = 3.6 V | ||
| Line 77: | Line 77: | ||
== Cache == | == Cache == | ||
{{main|exponential_technology/microarchitectures/x704#Memory_Hierarchy|l1=X704 § Cache}} | {{main|exponential_technology/microarchitectures/x704#Memory_Hierarchy|l1=X704 § Cache}} | ||
| − | Level 3 can be provided externally with cache size of 512 | + | Level 3 can be provided externally with cache size of 512 KiB to 2 MiB. |
{{cache info | {{cache info | ||
| − | |l1i cache=2 | + | |l1i cache=2 KiB |
| − | |l1i break=1x2 | + | |l1i break=1x2 KiB |
|l1i desc=direct mapped | |l1i desc=direct mapped | ||
|l1i extra= | |l1i extra= | ||
| − | |l1d cache=2 | + | |l1d cache=2 KiB |
| − | |l1d break=1x2 | + | |l1d break=1x2 KiB |
|l1d desc=direct mapped | |l1d desc=direct mapped | ||
|l1d extra= | |l1d extra= | ||
| − | |l2 cache=32 | + | |l2 cache=32 KiB |
| − | |l2 break=1x32 | + | |l2 break=1x32 KiB |
|l2 desc=8-way set associative | |l2 desc=8-way set associative | ||
|l2 extra= | |l2 extra= | ||
Latest revision as of 15:13, 13 December 2017
| Edit Values | |
| X704-410 | |
| General Info | |
| Designer | Exponential Technology |
| Manufacturer | Hitachi |
| Model Number | X704-410 |
| Market | Desktop |
| Introduction | March, 1997 (launched) |
| End-of-life | March, 1997 (last order) March, 1997 (last shipment) |
| General Specs | |
| Family | X704 |
| Frequency | 410 MHz |
| Bus type | 60x bus |
| Bus speed | 100 MHz |
| Clock multiplier | 4.1 |
| Microarchitecture | |
| Microarchitecture | X704 |
| Platform | CHRP |
| Process | 500 nm |
| Transistors | 2,700,000 |
| Technology | BiCMOS |
| Die | 150 mm² |
| Word Size | 32 bit |
| Cores | 1 |
| Threads | 1 |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Power dissipation | 85 W |
| Vcore | 3.6 V |
X704 410 MHz was a PowerPC-compatible microprocessor operating at 410 MHz introduced in February of 1997. This model was the final and only model actually produced by Exponential Technology in early 1997 with the plan of being implemented by Apple in their machines. The model was later dropped by Apple and faded into obscurity (See X704 § History).
Cache[edit]
- Main article: X704 § Cache
Level 3 can be provided externally with cache size of 512 KiB to 2 MiB.
| Cache Info [Edit Values] | ||
| L1I$ | 2 KiB 2,048 B 0.00195 MiB |
1x2 KiB direct mapped |
| L1D$ | 2 KiB 2,048 B 0.00195 MiB |
1x2 KiB direct mapped |
| L2$ | 32 KiB 0.0313 MiB 32,768 B 3.051758e-5 GiB |
1x32 KiB 8-way set associative |
Graphics[edit]
This SoC has no integrated graphics processing unit.
Features[edit]
- Fully PowerPC 60x-compatible architecture
- IEEE 1149.1-compliant JTAG test access port
- IEEE 754-compliant single-precision and double-precision arithmetic
- Support for standard PowerPC 60X bus with 64 bits of data and 32 bits of address
- Support for all PowerPC cache operations
- Support for PowerEndian and BigEndian modes
Documents[edit]
Manuals[edit]
- X704 Technical Summary, 1996
See also[edit]
Facts about "X704-410 - Exponential Technology"
| base frequency | 410 MHz (0.41 GHz, 410,000 kHz) + |
| bus speed | 100 MHz (0.1 GHz, 100,000 kHz) + |
| bus type | 60x bus + |
| clock multiplier | 4.1 + |
| core count | 1 + |
| core voltage | 3.6 V (36 dV, 360 cV, 3,600 mV) + |
| designer | Exponential Technology + |
| die area | 150 mm² (0.233 in², 1.5 cm², 150,000,000 µm²) + |
| family | X704 + |
| first launched | March 1997 + |
| full page name | exponential technology/x704/410 + |
| instance of | microprocessor + |
| l1d$ description | direct mapped + |
| l1d$ size | 2 KiB (2,048 B, 0.00195 MiB) + |
| l1i$ description | direct mapped + |
| l1i$ size | 2 KiB (2,048 B, 0.00195 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 0.0313 MiB (32 KiB, 32,768 B, 3.051758e-5 GiB) + |
| last order | March 1997 + |
| last shipment | March 1997 + |
| ldate | March 1997 + |
| manufacturer | Hitachi + |
| market segment | Desktop + |
| max cpu count | 1 + |
| microarchitecture | X704 + |
| model number | X704-410 + |
| name | X704-410 + |
| platform | CHRP + |
| power dissipation | 85 W (85,000 mW, 0.114 hp, 0.085 kW) + |
| process | 500 nm (0.5 μm, 5.0e-4 mm) + |
| smp max ways | 1 + |
| technology | BiCMOS + |
| thread count | 1 + |
| transistor count | 2,700,000 + |
| word size | 32 bit (4 octets, 8 nibbles) + |