From WikiChip
Difference between revisions of "cavium/octeon plus/cn5860-900bg1521-exp"
m (Bot: moving all {{mpu}} to {{chip}}) |
|||
(3 intermediate revisions by 2 users not shown) | |||
Line 1: | Line 1: | ||
{{cavium title|CN5860-900 EXP}} | {{cavium title|CN5860-900 EXP}} | ||
− | {{ | + | {{chip |
| name = Cavium CN5860-900 EXP | | name = Cavium CN5860-900 EXP | ||
| no image = | | no image = | ||
Line 10: | Line 10: | ||
| model number = CN5860-900 EXP | | model number = CN5860-900 EXP | ||
| part number = CN5860-900BG1521-EXP | | part number = CN5860-900BG1521-EXP | ||
− | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
+ | | part number 4 = | ||
| market = Network | | market = Network | ||
| first announced = October 9, 2006 | | first announced = October 9, 2006 | ||
Line 39: | Line 39: | ||
| core model = | | core model = | ||
| core stepping = | | core stepping = | ||
− | | process = | + | | process = 90 nm |
| transistors = | | transistors = | ||
| technology = CMOS | | technology = CMOS | ||
Line 78: | Line 78: | ||
| tambient max = | | tambient max = | ||
− | + | |package module 1={{packages/cavium/fcbga-1521}} | |
− | |||
− | |||
− | |||
− | | package | ||
− | |||
− | |||
− | |||
− | |||
− | |||
}} | }} | ||
'''CN5860-900 EXP''' is a {{arch|64}} [[hexadeca-core]] [[MIPS]] network microprocessor designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates sixteen {{cavium|cnMIPS|l=arch}} cores, operates at 900 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of various software such as [[RegEx]], compression/decompression, and TCP acceleration. | '''CN5860-900 EXP''' is a {{arch|64}} [[hexadeca-core]] [[MIPS]] network microprocessor designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates sixteen {{cavium|cnMIPS|l=arch}} cores, operates at 900 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of various software such as [[RegEx]], compression/decompression, and TCP acceleration. |
Latest revision as of 16:13, 13 December 2017
Edit Values | |||||||
Cavium CN5860-900 EXP | |||||||
![]() | |||||||
General Info | |||||||
Designer | Cavium | ||||||
Manufacturer | TSMC | ||||||
Model Number | CN5860-900 EXP | ||||||
Part Number | CN5860-900BG1521-EXP | ||||||
Market | Network | ||||||
Introduction | October 9, 2006 (announced) February, 2007 (launched) | ||||||
General Specs | |||||||
Family | OCTEON Plus | ||||||
Series | CN58xx | ||||||
Frequency | 900 MHz | ||||||
Microarchitecture | |||||||
ISA | MIPS64 (MIPS) | ||||||
Microarchitecture | cnMIPS | ||||||
Process | 90 nm | ||||||
Technology | CMOS | ||||||
Word Size | 64 bit | ||||||
Cores | 16 | ||||||
Threads | 16 | ||||||
Multiprocessing | |||||||
Max SMP | 1-Way (Uniprocessor) | ||||||
Packaging | |||||||
|
CN5860-900 EXP is a 64-bit hexadeca-core MIPS network microprocessor designed by Cavium and introduced in 2007. This processor, which incorporates sixteen cnMIPS cores, operates at 900 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of various software such as RegEx, compression/decompression, and TCP acceleration.
Contents
Cache[edit]
- Main article: cnMIPS § Cache
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||
|
Memory controller[edit]
![]() |
Integrated Memory Controller
|
|||||||||||||
|
Expansions[edit]
![]() |
Expansion Options
|
|||||||||||||||
|
Networking[edit]
![]() |
Networking
|
|||||||
|
Hardware Accelerators[edit]
[Edit/Modify Accelerators Info]
![]() |
Hardware Accelerators
|
|||||||||||||||||
|
Block diagram[edit]
Datasheet[edit]
Facts about "CN5860-900 EXP - Cavium"