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Difference between revisions of "cavium/octeon plus/cn5850-900bg1521-nsp"
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{{cavium title|CN5850-900 NSP}} | {{cavium title|CN5850-900 NSP}} | ||
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| name = Cavium CN5850-900 NSP | | name = Cavium CN5850-900 NSP | ||
| no image = | | no image = | ||
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| model number = CN5850-900 NSP | | model number = CN5850-900 NSP | ||
| part number = CN5850-900BG1521-NSP | | part number = CN5850-900BG1521-NSP | ||
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| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
+ | | part number 4 = | ||
| market = Network | | market = Network | ||
| first announced = October 9, 2006 | | first announced = October 9, 2006 | ||
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| core model = | | core model = | ||
| core stepping = | | core stepping = | ||
− | | process = | + | | process = 90 nm |
| transistors = | | transistors = | ||
| technology = CMOS | | technology = CMOS | ||
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}} | }} | ||
+ | '''CN5850-900 NSP''' is a {{arch|64}} [[dodeca-core]] [[MIPS]] network service microprocessor (NSP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates twelve {{cavium|cnMIPS|l=arch}} cores, operates at 900 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance network services software such as encryption, [[RegEx]], compression/decompression, and TCP acceleration. | ||
+ | |||
+ | |||
+ | == Cache == | ||
+ | {{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=576 KiB | ||
+ | |l1i cache=384 KiB | ||
+ | |l1i break=12x32 KiB | ||
+ | |l1i desc=64-way set associative | ||
+ | |l1d cache=192 KiB | ||
+ | |l1d break=12x16 KiB | ||
+ | |l1d desc=64-way set associative | ||
+ | |l2 cache=2 MiB | ||
+ | |l2 break=1x2 MiB | ||
+ | |l2 desc=8-way set associative | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR2-800 | ||
+ | |ecc=Yes | ||
+ | |max mem= | ||
+ | |controllers=1 | ||
+ | |channels=1 | ||
+ | |width=128 bit | ||
+ | |max bandwidth=11.92 GiB/s | ||
+ | |bandwidth schan=11.92 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | |pcix width=64 bit | ||
+ | |pcix clock=133.33 MHz | ||
+ | |pcix rate=1,017.25 MiB/s | ||
+ | |pcix extra=host or slave | ||
+ | |uart=yes | ||
+ | |uart ports=2 | ||
+ | |gp io=Yes | ||
+ | }} | ||
+ | |||
+ | == Networking == | ||
+ | {{network | ||
+ | |mii opts=Yes | ||
+ | |rgmii=yes | ||
+ | |rgmii ports=8 | ||
+ | |spi opts=Yes | ||
+ | |spi42=Yes | ||
+ | |spi42 ports=2 | ||
+ | }} | ||
+ | |||
+ | == Hardware Accelerators == | ||
+ | {{accelerators | ||
+ | |encryption=Yes | ||
+ | |encryption type=DES, 3DES, AES-GCM, AES up to 256, SHA1, SHA-2 up to SHA-512, RSA up to 8192, DH, KASUMI | ||
+ | |regex=Yes | ||
+ | |regex feature=32 Engines | ||
+ | |compression=Yes | ||
+ | |decompression=Yes | ||
+ | |tcp=Yes | ||
+ | |qos=Yes | ||
+ | }} | ||
+ | |||
+ | == Block diagram == | ||
+ | [[File:octeon plus cn58xx.png|750px]] | ||
+ | |||
+ | == Datasheet == | ||
+ | * [[:File:octeon plus cn58xx (rev 1.4).pdf|OCTEON CN58XX Processors Product Brief]] |
Latest revision as of 16:12, 13 December 2017
Edit Values | |||||||
Cavium CN5850-900 NSP | |||||||
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General Info | |||||||
Designer | Cavium | ||||||
Manufacturer | TSMC | ||||||
Model Number | CN5850-900 NSP | ||||||
Part Number | CN5850-900BG1521-NSP | ||||||
Market | Network | ||||||
Introduction | October 9, 2006 (announced) February, 2007 (launched) | ||||||
General Specs | |||||||
Family | OCTEON Plus | ||||||
Series | CN58xx | ||||||
Frequency | 900 MHz | ||||||
Microarchitecture | |||||||
ISA | MIPS64 (MIPS) | ||||||
Microarchitecture | cnMIPS | ||||||
Process | 90 nm | ||||||
Technology | CMOS | ||||||
Word Size | 64 bit | ||||||
Cores | 12 | ||||||
Threads | 12 | ||||||
Multiprocessing | |||||||
Max SMP | 1-Way (Uniprocessor) | ||||||
Packaging | |||||||
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CN5850-900 NSP is a 64-bit dodeca-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2007. This processor, which incorporates twelve cnMIPS cores, operates at 900 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance network services software such as encryption, RegEx, compression/decompression, and TCP acceleration.
Contents
Cache[edit]
- Main article: cnMIPS § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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Networking[edit]
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Networking
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Hardware Accelerators[edit]
[Edit/Modify Accelerators Info]
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Hardware Accelerators
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Block diagram[edit]
Datasheet[edit]
Facts about "CN5850-900 NSP - Cavium"