Difference between revisions of "cavium/octeon plus/cn5850-1000bg1521-exp"

	Edit Values
	Cavium CN5850-1000 EXP
	General Info
Designer	Cavium
Manufacturer	TSMC
Model Number	CN5850-1000 EXP
Part Number	CN5850-1000BG1521-EXP
Market	Network
Introduction	October 9, 2006 (announced); February, 2007 (launched)
	General Specs
Family	OCTEON Plus
Series	CN58xx
Frequency	1,000 MHz
	Microarchitecture
ISA	MIPS64 (MIPS)
Microarchitecture	cnMIPS
Process	90 nm
Technology	CMOS
Word Size	64 bit
Cores	12
Threads	12
	Multiprocessing
Max SMP	1-Way (Uniprocessor)
	Packaging
Package	FCBGA-1521 (BGA)
Ball Count	1521
Interconnect	BGA-1521

Latest revision as of 15:12, 13 December 2017

CN5850-1000 EXP is a 64-bit dodeca-core MIPS network microprocessor designed by Cavium and introduced in 2007. This processor, which incorporates twelve cnMIPS cores, operates at 1 GHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of various software such as RegEx, compression/decompression, and TCP acceleration.

Cache[edit]

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

576 KiB

589,824 B
0.563 MiB

L1I$	384 KiB 393,216 B 0.375 MiB	12x32 KiB	64-way set associative
L1D$	192 KiB 196,608 B 0.188 MiB	12x16 KiB	64-way set associative

L2$

2 MiB

2,048 KiB
2,097,152 B
0.00195 GiB

		1x2 MiB	8-way set associative

Memory controller[edit]

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR2-800
Supports ECC	Yes
Controllers	1
Channels	1
Width	128 bit
Max Bandwidth	11.92 GiB/s 12,206.08 MiB/s 12.799 GB/s 12,799.003 MB/s 0.0116 TiB/s 0.0128 TB/s
Bandwidth	Single 11.92 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

Expansion Options

PCI-X

Width	64 bit
Clock	133.33 MHz
Rate	1,017.25 MiB/s
Features	host or slave

UART

Ports	2

GP I/O	Yes

Networking[edit]

[Edit/Modify Network Info]

Networking

MII

RGMII	Yes (Ports: 8)

SPI

SPI-4.2	Yes (Ports: 2)

Hardware Accelerators[edit]

[Edit/Modify Accelerators Info]

Hardware Accelerators

RegEx

RegEx	Yes
Features	32 Engines

Networking

TCP	Yes
QoS	Yes

Compression

Compression	Yes
Decompression	Yes

Block diagram[edit]

Datasheet[edit]

OCTEON CN58XX Processors Product Brief

@@ Line 1: / Line 1: @@
 {{cavium title|CN5850-1000 EXP}}
-{{mpu
+{{chip
 | name                = Cavium CN5850-1000 EXP
 | no image            =
@@ Line 10: / Line 10: @@
 | model number        = CN5850-1000 EXP
 | part number         = CN5850-1000BG1521-EXP
-| part number 1       =
 | part number 2       =
 | part number 3       =
+| part number 4       =
 | market              = Network
 | first announced     = October 9, 2006

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	CN5850-1000 EXP - Cavium#package +
base frequency	1,000 MHz (1 GHz, 1,000,000 kHz) +
core count	12 +
designer	Cavium +
family	OCTEON Plus +
first announced	October 9, 2006 +
first launched	February 2007 +
full page name	cavium/octeon plus/cn5850-1000bg1521-exp +
has ecc memory support	true +
has hardware accelerators for data compression	true +
has hardware accelerators for data decompression	true +
has hardware accelerators for network quality of service processing	true +
has hardware accelerators for regular expression	true +
has hardware accelerators for tcp packet processing	true +
instance of	microprocessor +
isa	MIPS64 +
isa family	MIPS +
l1$ size	576 KiB (589,824 B, 0.563 MiB) +
l1d$ description	64-way set associative +
l1d$ size	192 KiB (196,608 B, 0.188 MiB) +
l1i$ description	64-way set associative +
l1i$ size	384 KiB (393,216 B, 0.375 MiB) +
l2$ description	8-way set associative +
l2$ size	2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldate	February 2007 +
main image	+
manufacturer	TSMC +
market segment	Network +
max cpu count	1 +
max memory bandwidth	11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels	1 +
microarchitecture	cnMIPS +
model number	CN5850-1000 EXP +
name	Cavium CN5850-1000 EXP +
package	FCBGA-1521 +
part number	CN5850-1000BG1521-EXP +
process	90 nm (0.09 μm, 9.0e-5 mm) +
series	CN58xx +
smp max ways	1 +
supported memory type	DDR2-800 +
technology	CMOS +
thread count	12 +
word size	64 bit (8 octets, 16 nibbles) +

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