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Difference between revisions of "cavium/octeon plus/cn5750-900bg1217-ssp"
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{{cavium title|CN5750-900 SSP}} | {{cavium title|CN5750-900 SSP}} | ||
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| name = Cavium CN5750-900 SSP | | name = Cavium CN5750-900 SSP | ||
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| model number = CN5750-900 SSP | | model number = CN5750-900 SSP | ||
| part number = CN5750-900BG1217-SSP | | part number = CN5750-900BG1217-SSP | ||
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| market = Storage | | market = Storage | ||
| first announced = Jun 26, 2007 | | first announced = Jun 26, 2007 | ||
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'''CN5750-900 SSP''' is a {{arch|64}} [[dodeca-core]] [[MIPS]] secure storage processor (SSP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates twelve {{cavium|cnMIPS|l=arch}} cores, operates at 900 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], encryption, networking, TCP & [[QoS]] acceleration. | '''CN5750-900 SSP''' is a {{arch|64}} [[dodeca-core]] [[MIPS]] secure storage processor (SSP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates twelve {{cavium|cnMIPS|l=arch}} cores, operates at 900 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], encryption, networking, TCP & [[QoS]] acceleration. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=576 KiB | ||
+ | |l1i cache=384 KiB | ||
+ | |l1i break=12x32 KiB | ||
+ | |l1d cache=192 KiB | ||
+ | |l1d break=12x16 KiB | ||
+ | |l2 cache=2 MiB | ||
+ | |l2 break=1x2 MiB | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR2-800 | ||
+ | |ecc=Yes | ||
+ | |max mem= | ||
+ | |controllers=1 | ||
+ | |channels=2 | ||
+ | |width=64 bit | ||
+ | |max bandwidth=11.92 GiB/s | ||
+ | |bandwidth schan=5.96 GiB/s | ||
+ | |bandwidth dchan=11.92 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | |pcie revision=1.0 | ||
+ | |pcie lanes=8 | ||
+ | |pcie config=x4 | ||
+ | |pcie config 2=x8 | ||
+ | |uart=yes | ||
+ | |gp io=Yes | ||
+ | }} | ||
+ | |||
+ | == Networking == | ||
+ | Interface options: | ||
+ | * 8-lanes [[PCIe]] + 8-lanes PCIe | ||
+ | * 8-lanes PCIe + 4 lanes PCIe + 4x [SGMII OR XAUI] | ||
+ | * 2x [4-lanes PCIe] + 2x [4x SGMII OR XAUI] | ||
+ | {{network | ||
+ | |mii opts=Yes | ||
+ | |sgmii=yes | ||
+ | |sgmii ports=4 | ||
+ | |xaui=1 | ||
+ | |xaui ports=1 | ||
+ | }} | ||
+ | |||
+ | == Hardware Accelerators == | ||
+ | {{accelerators | ||
+ | |encryption=Yes | ||
+ | |encryption type=3DES, AES-GCM, AES up to 256-bit, SHA-1, SHA-2 up to SHA-512, RSA up to 8192, DH | ||
+ | |compression=Yes | ||
+ | |decompression=Yes | ||
+ | |tcp=Yes | ||
+ | |qos=Yes | ||
+ | |raid=Yes | ||
+ | |raid5=Yes | ||
+ | |raid6=Yes | ||
+ | }} | ||
+ | |||
+ | == Block diagram == | ||
+ | [[File:cn57xx block diagram.png|750px]] | ||
+ | |||
+ | == Datasheet == | ||
+ | * [[:File:CN57XX PB Rev 1.2.pdf|OCTEON CN57XX Processors Product Brief]] |
Latest revision as of 16:12, 13 December 2017
Edit Values | |||||||||
Cavium CN5750-900 SSP | |||||||||
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General Info | |||||||||
Designer | Cavium | ||||||||
Manufacturer | TSMC | ||||||||
Model Number | CN5750-900 SSP | ||||||||
Part Number | CN5750-900BG1217-SSP | ||||||||
Market | Storage | ||||||||
Introduction | Jun 26, 2007 (announced) August, 2007 (launched) | ||||||||
General Specs | |||||||||
Family | OCTEON Plus | ||||||||
Series | CN57xx | ||||||||
Frequency | 900 MHz | ||||||||
Microarchitecture | |||||||||
ISA | MIPS64 (MIPS) | ||||||||
Microarchitecture | cnMIPS | ||||||||
Process | 90 nm | ||||||||
Technology | CMOS | ||||||||
Word Size | 64 bit | ||||||||
Cores | 12 | ||||||||
Threads | 12 | ||||||||
Multiprocessing | |||||||||
Max SMP | 1-Way (Uniprocessor) | ||||||||
Packaging | |||||||||
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CN5750-900 SSP is a 64-bit dodeca-core MIPS secure storage processor (SSP) designed by Cavium and introduced in 2007. This processor, which incorporates twelve cnMIPS cores, operates at 900 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, encryption, networking, TCP & QoS acceleration.
Contents
Cache[edit]
- Main article: cnMIPS § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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Networking[edit]
Interface options:
- 8-lanes PCIe + 8-lanes PCIe
- 8-lanes PCIe + 4 lanes PCIe + 4x [SGMII OR XAUI]
- 2x [4-lanes PCIe] + 2x [4x SGMII OR XAUI]
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Networking
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Hardware Accelerators[edit]
[Edit/Modify Accelerators Info]
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Hardware Accelerators
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Block diagram[edit]
Datasheet[edit]
Facts about "CN5750-900 SSP - Cavium"