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Difference between revisions of "cavium/octeon/cn3840-400bg1521-exp"
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| name = Cavium CN3840-400 EXP | | name = Cavium CN3840-400 EXP | ||
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| model number = CN3840-400 EXP | | model number = CN3840-400 EXP | ||
| part number = CN3840-400BG1521-EXP | | part number = CN3840-400BG1521-EXP | ||
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| market = Networking | | market = Networking | ||
| − | | first announced = | + | | first announced = August 22, 2005 |
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The '''CN3840-400 EXP''' is a {{arch|64}} [[octa-core]] [[MIPS]] communication [[microprocessor]] designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates eight {{cavium|cnMIPS|l=arch}} cores, operates at 400 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory. | The '''CN3840-400 EXP''' is a {{arch|64}} [[octa-core]] [[MIPS]] communication [[microprocessor]] designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates eight {{cavium|cnMIPS|l=arch}} cores, operates at 400 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory. | ||
Latest revision as of 16:11, 13 December 2017
| Edit Values | |||||||
| Cavium CN3840-400 EXP | |||||||
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| General Info | |||||||
| Designer | Cavium | ||||||
| Manufacturer | TSMC | ||||||
| Model Number | CN3840-400 EXP | ||||||
| Part Number | CN3840-400BG1521-EXP | ||||||
| Market | Networking | ||||||
| Introduction | August 22, 2005 (announced) August 22, 2005 (launched) | ||||||
| General Specs | |||||||
| Family | OCTEON | ||||||
| Series | CN3800 | ||||||
| Frequency | 400 MHz | ||||||
| Microarchitecture | |||||||
| ISA | MIPS64 (MIPS) | ||||||
| Microarchitecture | cnMIPS | ||||||
| Core Name | cnMIPS | ||||||
| Process | 130 nm | ||||||
| Technology | CMOS | ||||||
| Word Size | 64 bit | ||||||
| Cores | 8 | ||||||
| Threads | 8 | ||||||
| Max Memory | 16 GiB | ||||||
| Multiprocessing | |||||||
| Max SMP | 1-Way (Uniprocessor) | ||||||
| Packaging | |||||||
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The CN3840-400 EXP is a 64-bit octa-core MIPS communication microprocessor designed by Cavium and introduced in 2005. This processor, which incorporates eight cnMIPS cores, operates at 400 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
Contents
Cache[edit]
- Main article: cnMIPS § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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Networking[edit]
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Networking
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Hardware Accelerators[edit]
[Edit/Modify Accelerators Info]
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Hardware Accelerators
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Block diagram[edit]
Datasheet[edit]
Facts about "CN3840-400 EXP - Cavium"
