Semiconductor & Computer Engineering
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Difference between revisions of "amd/k5/amd-k5-pr75abr"
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{{amd title|AMD-K5-PR75ABR}} | {{amd title|AMD-K5-PR75ABR}} | ||
| − | {{ | + | {{chip |
| name = AMD-K5-PR75ABR | | name = AMD-K5-PR75ABR | ||
| no image = Yes | | no image = Yes | ||
| Line 10: | Line 10: | ||
| model number = AMD-K5-PR75ABR | | model number = AMD-K5-PR75ABR | ||
| part number = AMD-K5-PR75ABR | | part number = AMD-K5-PR75ABR | ||
| − | | part number | + | | part number 2 = |
| market = Desktop | | market = Desktop | ||
| first announced = 1996 | | first announced = 1996 | ||
| Line 42: | Line 42: | ||
| thread count = 1 | | thread count = 1 | ||
| max cpus = 1 | | max cpus = 1 | ||
| − | | max memory = 4 | + | | max memory = 4 GiB |
| max memory addr = 0xFFFFFFFF | | max memory addr = 0xFFFFFFFF | ||
| − | + | ||
| power = 11.8 W | | power = 11.8 W | ||
| v core = 3.525 V | | v core = 3.525 V | ||
| Line 77: | Line 77: | ||
== Cache == | == Cache == | ||
{{main|amd/microarchitectures/k5#Memory_Hierarchy|l1=K5 § Cache}} | {{main|amd/microarchitectures/k5#Memory_Hierarchy|l1=K5 § Cache}} | ||
| − | |||
{{cache info | {{cache info | ||
| − | |l1i cache=16 | + | |l1i cache=16 KiB |
| − | |l1i break=1x16 | + | |l1i break=1x16 KiB |
|l1i desc=4-way set associative | |l1i desc=4-way set associative | ||
|l1i extra= | |l1i extra= | ||
| − | |l1d cache=8 | + | |l1d cache=8 KiB |
| − | |l1d break=1x8 | + | |l1d break=1x8 KiB |
|l1d desc=4-way set associative | |l1d desc=4-way set associative | ||
|l1d extra= | |l1d extra= | ||
| Line 96: | Line 95: | ||
|l3 extra= | |l3 extra= | ||
}} | }} | ||
| + | |||
| + | == Die Shot == | ||
| + | [[File:AMD K5 PR75 die.JPG|650px]] | ||
== Graphics == | == Graphics == | ||
| Line 101: | Line 103: | ||
== Features == | == Features == | ||
| + | * [[processor p-rating::P75]] [[P-Rating]] | ||
* Auto-power down state | * Auto-power down state | ||
* Stop clock state | * Stop clock state | ||
Latest revision as of 15:08, 13 December 2017
| Edit Values | |
| AMD-K5-PR75ABR | |
| General Info | |
| Designer | AMD |
| Manufacturer | AMD |
| Model Number | AMD-K5-PR75ABR |
| Part Number | AMD-K5-PR75ABR |
| Market | Desktop |
| Introduction | 1996 (announced) October 7, 1996 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | K5 |
| Series | SSA/5 |
| Frequency | 75 MHz |
| Bus type | FSB |
| Bus speed | 50 MHz |
| Bus rate | 50 MT/s |
| Clock multiplier | 1.5 |
| CPUID | 501 |
| Microarchitecture | |
| Microarchitecture | K5 |
| Core Name | SSA/5 |
| Core Family | 5 |
| Core Model | 0 |
| Core Stepping | 1 |
| Process | 350 nm |
| Transistors | 4,300,000 |
| Technology | CMOS |
| Die | 161 mm² |
| Word Size | 32 bit |
| Cores | 1 |
| Threads | 1 |
| Max Memory | 4 GiB |
| Max Address Mem | 0xFFFFFFFF |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Power dissipation | 11.8 W |
| Vcore | 3.525 V ± 2% |
| Tcase | 0 °C – 70 °C |
| Tstorage | -65°C – 150 °C |
AMD-K5-PR75ABR was a 32-bit x86 microprocessor developed by AMD and released in 1996. This chip was sold as Pentium 75 MHz equivalent. The processor used AMD's 2nd revision of their K5 microarchitecture, operating at 75 MHz with a TDP of 11.8 W.
Contents
Cache[edit]
- Main article: K5 § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 16 KiB 16,384 B 0.0156 MiB |
1x16 KiB 4-way set associative |
| L1D$ | 8 KiB 8,192 B 0.00781 MiB |
1x8 KiB 4-way set associative |
Die Shot[edit]
Graphics[edit]
This SoC has no integrated graphics processing unit.
Features[edit]
- P75 P-Rating
- Auto-power down state
- Stop clock state
See also[edit]
Facts about "AMD-K5-PR75ABR - AMD"
| base frequency | 75 MHz (0.075 GHz, 75,000 kHz) + |
| bus rate | 50 MT/s (0.05 GT/s, 50,000 kT/s) + |
| bus speed | 50 MHz (0.05 GHz, 50,000 kHz) + |
| bus type | FSB + |
| clock multiplier | 1.5 + |
| core count | 1 + |
| core family | 5 + |
| core model | 0 + |
| core name | SSA/5 + |
| core stepping | 1 + |
| core voltage | 3.525 V (35.25 dV, 352.5 cV, 3,525 mV) + |
| core voltage tolerance | 2% + |
| cpuid | 501 + |
| designer | AMD + |
| die area | 161 mm² (0.25 in², 1.61 cm², 161,000,000 µm²) + |
| family | K5 + |
| first announced | 1996 + |
| first launched | October 7, 1996 + |
| full page name | amd/k5/amd-k5-pr75abr + |
| instance of | microprocessor + |
| l1d$ description | 4-way set associative + |
| l1d$ size | 8 KiB (8,192 B, 0.00781 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
| ldate | October 7, 1996 + |
| manufacturer | AMD + |
| market segment | Desktop + |
| max case temperature | 343.15 K (70 °C, 158 °F, 617.67 °R) + |
| max cpu count | 1 + |
| max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
| max memory address | 0xFFFFFFFF + |
| max storage temperature | 423.15 K (150 °C, 302 °F, 761.67 °R) + |
| microarchitecture | K5 + |
| min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
| min storage temperature | 208.15 K (-65 °C, -85 °F, 374.67 °R) + |
| model number | AMD-K5-PR75ABR + |
| name | AMD-K5-PR75ABR + |
| part number | AMD-K5-PR75ABR + |
| power dissipation | 11.8 W (11,800 mW, 0.0158 hp, 0.0118 kW) + |
| process | 350 nm (0.35 μm, 3.5e-4 mm) + |
| processor p-rating | P75 + |
| series | SSA/5 + |
| smp max ways | 1 + |
| technology | CMOS + |
| thread count | 1 + |
| transistor count | 4,300,000 + |
| word size | 32 bit (4 octets, 8 nibbles) + |