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    Difference between revisions of "amd/am486/am486dx4-100sv8b"    
                	
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| {{amd title|Am486DX4-100SV8B}} | {{amd title|Am486DX4-100SV8B}} | ||
| − | {{ | + | {{chip | 
| | name                = Am486DX4-100SV8B | | name                = Am486DX4-100SV8B | ||
| | no image            =   | | no image            =   | ||
| Line 10: | Line 10: | ||
| | model number        = Am486DX4-100SV8B | | model number        = Am486DX4-100SV8B | ||
| | part number         = A80486DX4-100SV8B | | part number         = A80486DX4-100SV8B | ||
| − | | part number  | + | | part number 2       = S80486DX4-100SV8B | 
| − | |||
| | part number 3       =   | | part number 3       =   | ||
| + | | part number 4       =  | ||
| | market              =   | | market              =   | ||
| | first announced     = 1995 | | first announced     = 1995 | ||
| Line 45: | Line 45: | ||
| | thread count        =   | | thread count        =   | ||
| | max cpus            = 1 | | max cpus            = 1 | ||
| − | | max memory          = 4  | + | | max memory          = 4 GiB | 
| | max memory addr     =   | | max memory addr     =   | ||
| − | + | ||
| | power               =   | | power               =   | ||
| | v core              = 3.3 V | | v core              = 3.3 V | ||
| Line 90: | Line 90: | ||
| {{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | {{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | ||
| {{cache info | {{cache info | ||
| − | |l1 cache=8  | + | |l1 cache=8 KiB | 
| − | |l1 break=1x8  | + | |l1 break=1x8 KiB | 
| |l1 desc=4-way set associative | |l1 desc=4-way set associative | ||
| |l1 extra=(unified, write-back policy) | |l1 extra=(unified, write-back policy) | ||
Latest revision as of 15:19, 13 December 2017
| Edit Values | |
| Am486DX4-100SV8B | |
|  | |
| Am486DX4-100SV8B | |
| General Info | |
| Designer | AMD | 
| Manufacturer | AMD | 
| Model Number | Am486DX4-100SV8B | 
| Part Number | A80486DX4-100SV8B, S80486DX4-100SV8B | 
| Introduction | 1995 (announced) March, 1996 (launched) | 
| Shop | Amazon | 
| General Specs | |
| Family | Am486 | 
| Series | Am486DX4S | 
| Frequency | 100 MHz | 
| Bus type | FSB | 
| Bus speed | 33 MHz | 
| Bus rate | 33 MT/s | 
| Clock multiplier | 3 | 
| Microarchitecture | |
| Microarchitecture | 80486 | 
| Core Name | Am486DX4S | 
| Process | 500 nm | 
| Technology | CMOS | 
| Word Size | 32 bit | 
| Cores | 1 | 
| Max Memory | 4 GiB | 
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) | 
| Electrical | |
| Vcore | 3.3 V ± 0.3 V | 
| OP Temperature | 0 °C – 85 °C | 
Am486DX4-100SV8B was an Enhanced Am486 microprocessor introduced by AMD in 1996. This processor had a clock multiplier of 3 having a frequency of 100 MHz with a bus frequency of 33 MHz. This "Enhanced" Am486 includes some other features such as SMM, stop-clock control, and write-back cache. AMD later introduced the Am486DX4-100SV16B which was identical but had its L1$ doubled to 16 KB.
Cache[edit]
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 8 KiB 8,192 B  0.00781 MiB | 1x8 KiB 4-way set associative (unified, write-back policy) | 
Graphics[edit]
This chip had no integrated graphics processing unit.
Features[edit]
- Stop-clock control
- System Management Mode (SMM)
Packaging[edit]
| Part | Package | 
|---|---|
| A80486DX4-100SV8B | CPGA-168 | 
| S80486DX4-100SV8B | SQFP-208 | 
Documents[edit]
Gallery[edit]
See also[edit]
Facts about "Am486DX4-100SV8B  - AMD"
| base frequency | 100 MHz (0.1 GHz, 100,000 kHz) + | 
| bus rate | 33 MT/s (0.033 GT/s, 33,000 kT/s) + | 
| bus speed | 33 MHz (0.033 GHz, 33,000 kHz) + | 
| bus type | FSB + | 
| clock multiplier | 3 + | 
| core count | 1 + | 
| core name | Am486DX4S + | 
| core voltage | 3.3 V (33 dV, 330 cV, 3,300 mV) + | 
| core voltage tolerance | 0.3 V + | 
| designer | AMD + | 
| family | Am486 + | 
| first announced | 1995 + | 
| first launched | March 1996 + | 
| full page name | amd/am486/am486dx4-100sv8b + | 
| has feature | System Management Mode + | 
| instance of | microprocessor + | 
| l1$ description | 4-way set associative + | 
| l1$ size | 8 KiB (8,192 B, 0.00781 MiB) + | 
| ldate | March 1996 + | 
| main image |  + | 
| main image caption | Am486DX4-100SV8B + | 
| manufacturer | AMD + | 
| max cpu count | 1 + | 
| max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + | 
| max operating temperature | 85 °C + | 
| microarchitecture | 80486 + | 
| min operating temperature | 0 °C + | 
| model number | Am486DX4-100SV8B + | 
| name | Am486DX4-100SV8B + | 
| part number | A80486DX4-100SV8B + and S80486DX4-100SV8B + | 
| process | 500 nm (0.5 μm, 5.0e-4 mm) + | 
| series | Am486DX4S + | 
| smp max ways | 1 + | 
| technology | CMOS + | 
| word size | 32 bit (4 octets, 8 nibbles) + | 
