Semiconductor & Computer Engineering
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Difference between revisions of "amd/am486/am486dx4-100nv8t"
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{{amd title|Am486DX4-100NV8T}} | {{amd title|Am486DX4-100NV8T}} | ||
| − | {{ | + | {{chip |
| name = Am486DX4-100NV8T | | name = Am486DX4-100NV8T | ||
| no image = | | no image = | ||
| − | | image = AMD | + | | image = Ic-photo-AMD--A80486DX4-100NV8T-(486-CPU).png |
| image size = | | image size = | ||
| caption = A80486DX4-100NV8T | | caption = A80486DX4-100NV8T | ||
| Line 10: | Line 10: | ||
| model number = Am486DX4-100NV8T | | model number = Am486DX4-100NV8T | ||
| part number = A80486DX4-100NV8T | | part number = A80486DX4-100NV8T | ||
| − | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
| + | | part number 4 = | ||
| market = Desktop | | market = Desktop | ||
| first announced = | | first announced = | ||
| Line 25: | Line 25: | ||
| bus type = FSB | | bus type = FSB | ||
| bus speed = 33 MHz | | bus speed = 33 MHz | ||
| − | | bus rate = | + | | bus rate = 33 MT/s |
| clock multiplier = 3 | | clock multiplier = 3 | ||
| cpuid = | | cpuid = | ||
| Line 46: | Line 46: | ||
| thread count = | | thread count = | ||
| max cpus = 1 | | max cpus = 1 | ||
| − | | max memory = 4 | + | | max memory = 4 GiB |
| max memory addr = | | max memory addr = | ||
| − | + | ||
| power = 2.6 W | | power = 2.6 W | ||
| v core = 3.3 V | | v core = 3.3 V | ||
| Line 77: | Line 77: | ||
| socket 0 3 type = | | socket 0 3 type = | ||
}} | }} | ||
| − | '''Am486DX2-100NV8T''' was an {{intel|80486}}-compatible microprocessor introduced by [[AMD]] in 1995 following the conclusion of the legal battle with Intel. This processor had a clock multiplier of 3 having base frequency of 100 MHz with a bus frequency of 33 MHz. This model is is a modified version of {{\\|Am486DX4-100V8T}} (and earlier {{\\|Am486DX4-100}}) that no longer included Intel's ICE microcode. | + | '''Am486DX2-100NV8T''' was an {{intel|80486}}-compatible microprocessor introduced by [[AMD]] in 1995 following the conclusion of the legal battle with Intel. This processor had a clock multiplier of 3 having base frequency of 100 MHz with a bus frequency of 33 MHz. This model is is a modified version of {{\\|Am486DX4-100V8T}} (and earlier {{\\|Am486DX4-100}}) that {{amd|Am486#Larger Cache & Post-lawsuit|no longer included Intel's ICE microcode}}. |
== Cache == | == Cache == | ||
{{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | {{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | ||
{{cache info | {{cache info | ||
| − | |l1 cache=8 | + | |l1 cache=8 KiB |
| − | |l1 break=1x8 | + | |l1 break=1x8 KiB |
|l1 desc=4-way set associative | |l1 desc=4-way set associative | ||
|l1 extra=(unified, write-through policy) | |l1 extra=(unified, write-through policy) | ||
| Line 97: | Line 97: | ||
<gallery> | <gallery> | ||
File:Amd-am486dx4-100-wt.jpg| | File:Amd-am486dx4-100-wt.jpg| | ||
| + | File:AMD Am486 DX4 100 NV8T CPU.jpg| | ||
| + | File:Ic-photo-AMD--AM486DX4-100-(486-CPU).png| | ||
</gallery> | </gallery> | ||
Latest revision as of 14:19, 13 December 2017
| Edit Values | |
| Am486DX4-100NV8T | |
 | |
| A80486DX4-100NV8T | |
| General Info | |
| Designer | AMD |
| Manufacturer | AMD |
| Model Number | Am486DX4-100NV8T |
| Part Number | A80486DX4-100NV8T |
| Market | Desktop |
| Introduction | 1995 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | Am486 |
| Series | Am486DX4V |
| Frequency | 100 MHz |
| Bus type | FSB |
| Bus speed | 33 MHz |
| Bus rate | 33 MT/s |
| Clock multiplier | 3 |
| Microarchitecture | |
| Microarchitecture | 80486 |
| Core Name | 486DX4V |
| Process | 500 nm |
| Technology | CMOS |
| Word Size | 32 bit |
| Cores | 1 |
| Max Memory | 4 GiB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Power dissipation | 2.6 W |
| Vcore | 3.3 V ± 0.3 V |
| OP Temperature | 0 °C – 85 °C |
Am486DX2-100NV8T was an 80486-compatible microprocessor introduced by AMD in 1995 following the conclusion of the legal battle with Intel. This processor had a clock multiplier of 3 having base frequency of 100 MHz with a bus frequency of 33 MHz. This model is is a modified version of Am486DX4-100V8T (and earlier Am486DX4-100) that no longer included Intel's ICE microcode.
Cache[edit]
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 8 KiB 8,192 B 0.00781 MiB |
1x8 KiB 4-way set associative (unified, write-through policy) |
Graphics[edit]
This chip had no integrated graphics processing unit.
Documents[edit]
Gallery[edit]
.png)
Die Shot[edit]
See also[edit]
Facts about "Am486DX4-100NV8T - AMD"
| base frequency | 100 MHz (0.1 GHz, 100,000 kHz) + |
| bus rate | 33 MT/s (0.033 GT/s, 33,000 kT/s) + |
| bus speed | 33 MHz (0.033 GHz, 33,000 kHz) + |
| bus type | FSB + |
| clock multiplier | 3 + |
| core count | 1 + |
| core name | 486DX4V + |
| core voltage | 3.3 V (33 dV, 330 cV, 3,300 mV) + |
| core voltage tolerance | 0.3 V + |
| designer | AMD + |
| family | Am486 + |
| first launched | 1995 + |
| full page name | amd/am486/am486dx4-100nv8t + |
| instance of | microprocessor + |
| l1$ description | 4-way set associative + |
| l1$ size | 8 KiB (8,192 B, 0.00781 MiB) + |
| ldate | 1995 + |
| main image | .png) + |
| main image caption | A80486DX4-100NV8T + |
| manufacturer | AMD + |
| market segment | Desktop + |
| max cpu count | 1 + |
| max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
| max operating temperature | 85 °C + |
| microarchitecture | 80486 + |
| min operating temperature | 0 °C + |
| model number | Am486DX4-100NV8T + |
| name | Am486DX4-100NV8T + |
| part number | A80486DX4-100NV8T + |
| power dissipation | 2.6 W (2,600 mW, 0.00349 hp, 0.0026 kW) + |
| process | 500 nm (0.5 μm, 5.0e-4 mm) + |
| series | Am486DX4V + |
| smp max ways | 1 + |
| technology | CMOS + |
| word size | 32 bit (4 octets, 8 nibbles) + |
.png){kind=link}