Semiconductor & Computer Engineering
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Difference between revisions of "amd/am486/am486dx2-50"
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{{amd title|Am486DX2-50}} | {{amd title|Am486DX2-50}} | ||
| − | {{ | + | {{chip |
| name = Am486DX2-50 | | name = Am486DX2-50 | ||
| − | |||
| image = | | image = | ||
| image size = | | image size = | ||
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| model number = Am486DX2-50 | | model number = Am486DX2-50 | ||
| part number = A80486DX2-50 | | part number = A80486DX2-50 | ||
| − | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
| + | | part number 4 = | ||
| market = Desktop | | market = Desktop | ||
| first announced = April, 1993 | | first announced = April, 1993 | ||
| Line 25: | Line 24: | ||
| bus type = FSB | | bus type = FSB | ||
| bus speed = 25 MHz | | bus speed = 25 MHz | ||
| − | | bus rate = | + | | bus rate = 25 MT/s |
| clock multiplier = 2 | | clock multiplier = 2 | ||
| cpuid = | | cpuid = | ||
| Line 47: | Line 46: | ||
| thread count = | | thread count = | ||
| max cpus = 1 | | max cpus = 1 | ||
| − | | max memory = 4 | + | | max memory = 4 GiB |
| max memory addr = | | max memory addr = | ||
| − | + | ||
| power = | | power = | ||
| v core = 5 V | | v core = 5 V | ||
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{{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | {{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | ||
{{cache info | {{cache info | ||
| − | |l1 cache=8 | + | |l1 cache=8 KiB |
| − | |l1 break=1x8 | + | |l1 break=1x8 KiB |
|l1 desc=4-way set associative | |l1 desc=4-way set associative | ||
|l1 extra=(unified, write-through policy) | |l1 extra=(unified, write-through policy) | ||
Latest revision as of 14:18, 13 December 2017
| Edit Values | |
| Am486DX2-50 | |
 | |
| General Info | |
| Designer | AMD |
| Manufacturer | AMD |
| Model Number | Am486DX2-50 |
| Part Number | A80486DX2-50 |
| Market | Desktop |
| Introduction | April, 1993 (announced) June, 1993 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | Am486 |
| Series | Am486DX2 |
| Frequency | 50 MHz |
| Bus type | FSB |
| Bus speed | 25 MHz |
| Bus rate | 25 MT/s |
| Clock multiplier | 2 |
| Microarchitecture | |
| Microarchitecture | 80486 |
| Core Name | 486DX2 |
| Process | 700 nm, 500 nm |
| Transistors | 1,200,000 |
| Technology | CMOS |
| Word Size | 32 bit |
| Cores | 1 |
| Max Memory | 4 GiB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Vcore | 5 V |
| OP Temperature | 0 °C – 85 °C |
Am486DX2-50 was an 80486-compatible microprocessor introduced by AMD in 1993. This processor had a clock multiplier of 2 having base frequency of 50 MHz with a FSB frequency of 25 MHz.
Cache[edit]
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 8 KiB 8,192 B 0.00781 MiB |
1x8 KiB 4-way set associative (unified, write-through policy) |
Graphics[edit]
This chip had no integrated graphics processing unit.
See also[edit]
Facts about "Am486DX2-50 - AMD"
| base frequency | 50 MHz (0.05 GHz, 50,000 kHz) + |
| bus rate | 25 MT/s (0.025 GT/s, 25,000 kT/s) + |
| bus speed | 25 MHz (0.025 GHz, 25,000 kHz) + |
| bus type | FSB + |
| clock multiplier | 2 + |
| core count | 1 + |
| core name | 486DX2 + |
| core voltage | 5 V (50 dV, 500 cV, 5,000 mV) + |
| designer | AMD + |
| family | Am486 + |
| first announced | April 1993 + |
| first launched | June 1993 + |
| full page name | amd/am486/am486dx2-50 + |
| instance of | microprocessor + |
| l1$ description | 4-way set associative + |
| l1$ size | 8 KiB (8,192 B, 0.00781 MiB) + |
| ldate | June 1993 + |
| manufacturer | AMD + |
| market segment | Desktop + |
| max cpu count | 1 + |
| max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
| max operating temperature | 85 °C + |
| microarchitecture | 80486 + |
| min operating temperature | 0 °C + |
| model number | Am486DX2-50 + |
| name | Am486DX2-50 + |
| part number | A80486DX2-50 + |
| process | 700 nm (0.7 μm, 7.0e-4 mm) + and 500 nm (0.5 μm, 5.0e-4 mm) + |
| series | Am486DX2 + |
| smp max ways | 1 + |
| technology | CMOS + |
| transistor count | 1,200,000 + |
| word size | 32 bit (4 octets, 8 nibbles) + |