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{{ambric title|Am2045B}}
 
{{ambric title|Am2045B}}
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{{mpu
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{{chip
 
| name                = Am2045B
 
| name                = Am2045B
 
| no image            = Yes
 
| no image            = Yes
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| frequency          = 350 MHz
 
| frequency          = 350 MHz
 
| bus type            =  
 
| bus type            =  
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| bus speed          =  
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| bus speed          = 100 MHz
 
| bus rate            =  
 
| bus rate            =  
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| clock multiplier    =  
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| clock multiplier    = 3.5
  
 
| microarch          = Ambric  
 
| microarch          = Ambric  
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| die size            =  
 
| die size            =  
 
| word size          = 32 bit
 
| word size          = 32 bit
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| core count          = 336
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| core count          = 344
 
| thread count        =  
 
| thread count        =  
 
| max cpus            =  
 
| max cpus            =  
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| max memory          =  
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| max memory          = 4 GiB
  
 
| electrical          =  
 
| electrical          =  
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| socket 0 type      = BGA
 
| socket 0 type      = BGA
 
}}
 
}}
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'''Am2045B''' was [[Ambric]]'s flagship [[MPPA]] introduced in late 2007. This model was made of {{ambric|am2000#Architecture|43 Brics}} arranged as a grid, making up a total of 344 {{arch|32}} [[RICS]]-like cores operating asynchronously at 1-350 MHz. This was an enhanced version of the {{\\|Am2045|original}} which featured a higher bandwidth [[network on a chip]] (Ambric claimed up to 40 percent improvement), operated at higher frequency, and provided up to 1.2 trillion operations per seconds theoretical peak computation. This model also had lower power consumption over the original.
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Note that some early models might have had only 42 brics at one point for 336 cores.
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== Architecture ==
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{{main|ambric/am2000#Architecture|l1=Am2000 § Architecture}}
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The Am2045B is made of 43 homogeneous 'Brics' laid out in a grid to form 344 cores.
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General layout:
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* 43x Brics
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** 2x Computer Unit (CU)
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*** 2x SRD {{arch|32}} CPU
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*** 2x RD {{arch|32}} CPU
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** 2x [[RAM]] Unit (RU)
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*** 4x 2 KB [[SRAM]] bank
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== Memory controller ==
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{{integrated memory controller
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| type              = DDR2-400
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| controllers        = 2
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| channels          = 1
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| ecc support        =
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| max bandwidth      =
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| bandwidth schan    =
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| bandwidth dchan    =
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| max memory        = 4 GiB
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}}
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== Expansions ==
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* [[has feature::PCIe]]
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* [[has feature::JTAG]]
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* 128x [[has feature::GPIO]] @ 100 MHz
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* [[has feature::serial flash]]
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== Die Shot ==
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{|
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| [[File:Am2045 die shot.png]]  || [[File:Am2045 die shot (annotated).png]]
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|}

Latest revision as of 14:16, 13 December 2017

Edit Values
Am2045B
General Info
DesignerAmbric
Model NumberAm2045B
Part NumberAm2045B
MarketEmbedded
IntroductionNovember 15, 2007 (announced)
November 15, 2007 (launched)
End-of-life2012 (last order)
2012 (last shipment)
General Specs
FamilyAm2000
SeriesGen 2
LockedNo
Frequency350 MHz
Bus speed100 MHz
Clock multiplier3.5
Microarchitecture
MicroarchitectureAmbric
Process130 nm
Transistors180,000,000
TechnologyCMOS
Word Size32 bit
Cores344
Max Memory4 GiB

Am2045B was Ambric's flagship MPPA introduced in late 2007. This model was made of 43 Brics arranged as a grid, making up a total of 344 32-bit RICS-like cores operating asynchronously at 1-350 MHz. This was an enhanced version of the original which featured a higher bandwidth network on a chip (Ambric claimed up to 40 percent improvement), operated at higher frequency, and provided up to 1.2 trillion operations per seconds theoretical peak computation. This model also had lower power consumption over the original.

Note that some early models might have had only 42 brics at one point for 336 cores.

Architecture[edit]

Main article: Am2000 § Architecture

The Am2045B is made of 43 homogeneous 'Brics' laid out in a grid to form 344 cores.

General layout:

  • 43x Brics

Memory controller[edit]

Integrated Memory Controller
Type DDR2-400
Controllers 2
Channels 1
Max memory 4 GiB

Expansions[edit]

  • PCIe
  • JTAG
  • 128x GPIO @ 100 MHz
  • serial flash

Die Shot[edit]

Am2045 die shot.png Am2045 die shot (annotated).png
Retrieved from "https://en.wikichip.org/w/index.php?title=ambric/am2000/am2045b&oldid=69231"
Facts about "Am2045B - Ambric"
RDF feed
base frequency350 MHz (0.35 GHz, 350,000 kHz) +
bus speed100 MHz (0.1 GHz, 100,000 kHz) +
clock multiplier3.5 +
core count344 +
designerAmbric +
familyAm2000 +
first announcedNovember 15, 2007 +
first launchedNovember 15, 2007 +
full page nameambric/am2000/am2045b +
has featurePCIe +, JTAG +, GPIO + and serial flash +
has locked clock multiplierfalse +
instance ofmicroprocessor +
last order2012 +
last shipment2012 +
ldateNovember 15, 2007 +
market segmentEmbedded +
max memory4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
microarchitectureAmbric +
model numberAm2045B +
nameAm2045B +
part numberAm2045B +
process130 nm (0.13 μm, 1.3e-4 mm) +
seriesGen 2 +
technologyCMOS +
transistor count180,000,000 +
word size32 bit (4 octets, 8 nibbles) +