Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "ambric/am2000/am2024"
(Created page with "{{ambric title|Am2024}} {{mpu | name = Am2024 | no image = Yes | image = | image size = | caption = | designer...") |
m (Bot: switching template from {{mpu}} to a more generic {{chip}}) |
||
| (5 intermediate revisions by 2 users not shown) | |||
| Line 1: | Line 1: | ||
{{ambric title|Am2024}} | {{ambric title|Am2024}} | ||
| − | {{ | + | {{chip |
| name = Am2024 | | name = Am2024 | ||
| no image = Yes | | no image = Yes | ||
| Line 8: | Line 8: | ||
| designer = Ambric | | designer = Ambric | ||
| manufacturer = | | manufacturer = | ||
| − | | model number = | + | | model number = Am2024 |
| part number = Am2024 | | part number = Am2024 | ||
| market = Embedded | | market = Embedded | ||
| Line 21: | Line 21: | ||
| frequency = 333 MHz | | frequency = 333 MHz | ||
| bus type = | | bus type = | ||
| − | | bus speed = | + | | bus speed = 100 MHz |
| bus rate = | | bus rate = | ||
| − | | clock multiplier = | + | | clock multiplier = 3.3 |
| microarch = Ambric | | microarch = Ambric | ||
| Line 40: | Line 40: | ||
| thread count = | | thread count = | ||
| max cpus = | | max cpus = | ||
| − | | max memory = | + | | max memory = 4 GiB |
| electrical = | | electrical = | ||
| Line 72: | Line 72: | ||
| socket 0 type = | | socket 0 type = | ||
}} | }} | ||
| + | '''Am2024''' was an [[MPPA]] introduced in late 2006 by [[Ambric]]. This model was made of {{ambric|am2000#Architecture|24 Brics}} arranged as a grid, making up a total of 192 {{arch|32}} [[RICS]]-like cores operating asynchronously at 1-333 MHz. | ||
| + | |||
| + | == Architecture == | ||
| + | {{main|ambric/am2000#Architecture|l1=Am2000 § Architecture}} | ||
| + | The Am2024 is made of 24 homogeneous 'Brics' laid out in a grid to form 192 cores and 192 RAM units. | ||
| + | |||
| + | General layout: | ||
| + | * 24x Brics | ||
| + | ** 2x Computer Unit (CU) | ||
| + | *** 2x SRD {{arch|32}} CPU | ||
| + | *** 2x RD {{arch|32}} CPU | ||
| + | ** 2x [[RAM]] Unit (RU) | ||
| + | *** 4x 2 KB [[SRAM]] bank | ||
| + | |||
| + | == Cache == | ||
| + | The Am2035 contains 24 Brics, each with its own [[RAM]] Unit (RU) of 13 kB of SRAM for a total of 312 kB of SRAM. | ||
| + | |||
| + | == Memory controller == | ||
| + | {{integrated memory controller | ||
| + | | type = DDR2-400 | ||
| + | | controllers = 2 | ||
| + | | channels = 1 | ||
| + | | ecc support = | ||
| + | | max bandwidth = | ||
| + | | bandwidth schan = | ||
| + | | bandwidth dchan = | ||
| + | | max memory = 4 GiB | ||
| + | }} | ||
| + | |||
| + | == Expansions == | ||
| + | * [[has feature::PCIe]] | ||
| + | * [[has feature::JTAG]] | ||
| + | * [[has feature::GPIO]] @ 100 MHz | ||
| + | * [[has feature::serial flash]] | ||
Latest revision as of 14:16, 13 December 2017
| Edit Values | |
| Am2024 | |
| General Info | |
| Designer | Ambric |
| Model Number | Am2024 |
| Part Number | Am2024 |
| Market | Embedded |
| Introduction | October 10, 2006 (announced) January 2007 (launched) |
| End-of-life | 2012 (last order) 2012 (last shipment) |
| General Specs | |
| Family | Am2000 |
| Series | Gen 1 |
| Locked | No |
| Frequency | 333 MHz |
| Bus speed | 100 MHz |
| Clock multiplier | 3.3 |
| Microarchitecture | |
| Microarchitecture | Ambric |
| Process | 130 nm |
| Technology | CMOS |
| Word Size | 32 bit |
| Cores | 192 |
| Max Memory | 4 GiB |
Am2024 was an MPPA introduced in late 2006 by Ambric. This model was made of 24 Brics arranged as a grid, making up a total of 192 32-bit RICS-like cores operating asynchronously at 1-333 MHz.
Architecture[edit]
- Main article: Am2000 § Architecture
The Am2024 is made of 24 homogeneous 'Brics' laid out in a grid to form 192 cores and 192 RAM units.
General layout:
- 24x Brics
Cache[edit]
The Am2035 contains 24 Brics, each with its own RAM Unit (RU) of 13 kB of SRAM for a total of 312 kB of SRAM.
Memory controller[edit]
| Integrated Memory Controller | |
| Type | DDR2-400 |
| Controllers | 2 |
| Channels | 1 |
| Max memory | 4 GiB |
Expansions[edit]
- PCIe
- JTAG
- GPIO @ 100 MHz
- serial flash
Facts about "Am2024 - Ambric"
| base frequency | 333 MHz (0.333 GHz, 333,000 kHz) + |
| bus speed | 100 MHz (0.1 GHz, 100,000 kHz) + |
| clock multiplier | 3.3 + |
| core count | 192 + |
| designer | Ambric + |
| family | Am2000 + |
| first announced | October 10, 2006 + |
| first launched | January 2007 + |
| full page name | ambric/am2000/am2024 + |
| has feature | PCIe +, JTAG +, GPIO + and serial flash + |
| has locked clock multiplier | false + |
| instance of | microprocessor + |
| last order | 2012 + |
| last shipment | 2012 + |
| ldate | January 2007 + |
| market segment | Embedded + |
| max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
| microarchitecture | Ambric + |
| model number | Am2024 + |
| name | Am2024 + |
| part number | Am2024 + |
| process | 130 nm (0.13 μm, 1.3e-4 mm) + |
| series | Gen 1 + |
| technology | CMOS + |
| word size | 32 bit (4 octets, 8 nibbles) + |