Semiconductor & Computer Engineering
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{{title|RISC-V}}{{risc-v isa main}} | {{title|RISC-V}}{{risc-v isa main}} | ||
'''RISC-V''' (pronounced ''risk-five'') is a free and open [[instruction set architecture]] standardized by the {{risc-v|Foundation|RISC-V Foundation}} that is specifically designed to enable configurability, modularity, and extensibility. RISC-V is not designed to replace prominent ISAs such as [[x86]] and [[ARM]], but rather to provide a foundation for emerging classes of [[processors]] and [[accelerators]] that require a base ISA on top of which additional functionality can be added. | '''RISC-V''' (pronounced ''risk-five'') is a free and open [[instruction set architecture]] standardized by the {{risc-v|Foundation|RISC-V Foundation}} that is specifically designed to enable configurability, modularity, and extensibility. RISC-V is not designed to replace prominent ISAs such as [[x86]] and [[ARM]], but rather to provide a foundation for emerging classes of [[processors]] and [[accelerators]] that require a base ISA on top of which additional functionality can be added. | ||
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| + | == Overview == | ||
| + | RISC-V is a free and open ISA; no license is needed to be obtained and the use of the ISA royalty-free for anyone. RISC-V is designed to provide a foundation or a base architecture for companies and researchers who need it in order to be able to augment their own technology (e.g., customer [[accelerators]], fixed function hardware, and other domain-specific additions) on top of it. RISC-V provides a base architecture (offered in 3 flavors of 32/64/128 bit) consisting of less than 50 instructions which is capable of running a full software stack including a full-fledged operating system. The core instructions are frozen and are guaranteed to never change. In addition to the core instructions, RISC-V provides a number of optional standard extensions that can be implemented or omitted depending on the designer goals. Other than the standard extensions RISC-V also reserves opcodes to be custom tailored by chip designers for their own applications. | ||
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[[category:instruction set architectures]] | [[category:instruction set architectures]] | ||
[[category:risc-v]] | [[category:risc-v]] | ||
Revision as of 04:21, 11 December 2017
Instruction Set Architecture
- Foundation
- Non-Standard Extensions
- Addressing Modes
- Registers
- Assembly
- Interrupts
- Microarchitectures
RISC-V (pronounced risk-five) is a free and open instruction set architecture standardized by the RISC-V Foundation that is specifically designed to enable configurability, modularity, and extensibility. RISC-V is not designed to replace prominent ISAs such as x86 and ARM, but rather to provide a foundation for emerging classes of processors and accelerators that require a base ISA on top of which additional functionality can be added.
Overview
RISC-V is a free and open ISA; no license is needed to be obtained and the use of the ISA royalty-free for anyone. RISC-V is designed to provide a foundation or a base architecture for companies and researchers who need it in order to be able to augment their own technology (e.g., customer accelerators, fixed function hardware, and other domain-specific additions) on top of it. RISC-V provides a base architecture (offered in 3 flavors of 32/64/128 bit) consisting of less than 50 instructions which is capable of running a full software stack including a full-fledged operating system. The core instructions are frozen and are guaranteed to never change. In addition to the core instructions, RISC-V provides a number of optional standard extensions that can be implemented or omitted depending on the designer goals. Other than the standard extensions RISC-V also reserves opcodes to be custom tailored by chip designers for their own applications.